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Mon, 19 Jul 2021 13:22:06 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:22:05 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:50:00 +0530 Message-Id: <20210719132012.150948-50-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: t-kbXs3VKkYoQO8HIIq9SmCNmaxRNQzu X-Proofpoint-GUID: t-kbXs3VKkYoQO8HIIq9SmCNmaxRNQzu X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=952 mlxscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 49/61] hw/phb5: Update PHB numbering to allow for virtual PHBs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat Make room for a per-chip numbering of virtual PHBs used by opencapi. We can have up to 12 opencapi PHBs (two per PAU) on P10. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- include/phb4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/phb4.h b/include/phb4.h index 217f68462..0bbfc926c 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -245,9 +245,9 @@ static inline void phb4_set_err_pending(struct phb4 *p, bool pending) p->err_pending = pending; } -#define MAX_PHBS_PER_CHIP_P10 6 /* Max 6 PHBs per chip on p10 */ #define MAX_PHBS_PER_CHIP_P9 6 /* Max 6 PHBs per chip on p9 */ #define MAX_PHBS_PER_CHIP_P9P 0x10 /* extra for virt PHBs */ +#define MAX_PHBS_PER_CHIP_P10 0x12 /* 6 PCI + 12 opencapi */ static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index) {