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Mon, 19 Jul 2021 13:21:34 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:21:34 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:49:44 +0530 Message-Id: <20210719132012.150948-34-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: uPnxDCTEGMLSH6_LhWnuSD08Sjnv3ge_ X-Proofpoint-ORIG-GUID: uPnxDCTEGMLSH6_LhWnuSD08Sjnv3ge_ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=903 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 mlxscore=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 33/61] psi/p10: Activate StoreEOI X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 15 ++++++++++++++- include/psi.h | 1 + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/psi.c b/hw/psi.c index 991ea3b1f..291422539 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -749,11 +749,14 @@ static const struct irq_source_ops psi_p10_irq_ops = { .name = psi_p9_irq_name, }; +#define PSIHB10_CAN_STORE_EOI(x) XIVE2_STORE_EOI_ENABLED + static void psi_init_p10_interrupts(struct psi *psi) { struct proc_chip *chip; u64 val; uint32_t esb_shift = 16; + uint32_t flags = XIVE_SRC_LSI; /* Grab chip */ chip = get_chip(psi->chip_id); @@ -772,6 +775,16 @@ static void psi_init_p10_interrupts(struct psi *psi) prlog(PR_DEBUG, "PSI[0x%03x]: ESB MMIO at @%p\n", psi->chip_id, psi->esb_mmio); + /* Store EOI */ + if (PSIHB10_CAN_STORE_EOI(psi)) { + val = in_be64(psi->regs + PSIHB_CR); + val |= PSIHB10_CR_STORE_EOI; + out_be64(psi->regs + PSIHB_CR, val); + prlog(PR_DEBUG, "PSI[0x%03x]: store EOI is enabled\n", + psi->chip_id); + flags |= XIVE_SRC_STORE_EOI; + } + /* Grab and configure the notification port */ val = xive2_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); val |= PSIHB_ESB_NOTIF_VALID; @@ -788,7 +801,7 @@ static void psi_init_p10_interrupts(struct psi *psi) psi->chip_id, 0xf & (chip->ec_level >> 4), chip->ec_level & 0xf); xive2_register_hw_source(psi->interrupt, P9_PSI_NUM_IRQS, - esb_shift, psi->esb_mmio, XIVE_SRC_LSI, + esb_shift, psi->esb_mmio, flags, psi, &psi_p10_irq_ops); /* Reset irq handling and switch to ESB mode */ diff --git a/include/psi.h b/include/psi.h index dbf94b4b3..ac7afa09f 100644 --- a/include/psi.h +++ b/include/psi.h @@ -41,6 +41,7 @@ #define PSIHB_CR_PSI_LINK_ENABLE PPC_BIT(5) #define PSIHB_CR_FSP_RESET PPC_BIT(6) #define PSIHB_CR_PSIHB_RESET PPC_BIT(7) +#define PSIHB10_CR_STORE_EOI PPC_BIT(12) #define PSIHB_CR_PSI_IRQ PPC_BIT(16) /* PSIHB interrupt */ #define PSIHB_CR_FSP_IRQ PPC_BIT(17) /* FSP interrupt */ #define PSIHB_CR_FSP_LINK_ACTIVE PPC_BIT(18) /* FSP link active */