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Mon, 19 Jul 2021 13:21:33 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:21:32 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:49:43 +0530 Message-Id: <20210719132012.150948-33-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: PUXsrwWPB61UVYzEdUx_MERQlLraX1IM X-Proofpoint-GUID: PUXsrwWPB61UVYzEdUx_MERQlLraX1IM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 32/61] psi/p10: Activate 64K ESB pages X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 7 ++++--- include/psi.h | 5 +++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index 26677a3b2..991ea3b1f 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -753,8 +753,7 @@ static void psi_init_p10_interrupts(struct psi *psi) { struct proc_chip *chip; u64 val; - /* TODO (clg) : fix ESB page size to 64k when ready */ - uint32_t esb_shift = 12; + uint32_t esb_shift = 16; /* Grab chip */ chip = get_chip(psi->chip_id); @@ -764,10 +763,12 @@ static void psi_init_p10_interrupts(struct psi *psi) /* Configure the CI BAR */ phys_map_get(chip->id, PSIHB_ESB, 0, &val, NULL); val |= PSIHB_ESB_CI_VALID; + if (esb_shift == 16) + val |= PSIHB10_ESB_CI_64K; out_be64(psi->regs + PSIHB_ESB_CI_BASE, val); val = in_be64(psi->regs + PSIHB_ESB_CI_BASE); - psi->esb_mmio = (void *)(val & ~PSIHB_ESB_CI_VALID); + psi->esb_mmio = (void *)(val & ~(PSIHB_ESB_CI_VALID|PSIHB10_ESB_CI_64K)); prlog(PR_DEBUG, "PSI[0x%03x]: ESB MMIO at @%p\n", psi->chip_id, psi->esb_mmio); diff --git a/include/psi.h b/include/psi.h index a7104ef0b..dbf94b4b3 100644 --- a/include/psi.h +++ b/include/psi.h @@ -94,9 +94,10 @@ #define PSIHB_IRQ_METHOD PPC_BIT(0) #define PSIHB_IRQ_RESET PPC_BIT(1) #define PSIHB_ESB_CI_BASE 0x60 -#define PSIHB_ESB_CI_VALID 1 +#define PSIHB10_ESB_CI_64K PPC_BIT(1) +#define PSIHB_ESB_CI_VALID PPC_BIT(63) #define PSIHB_ESB_NOTIF_ADDR 0x68 -#define PSIHB_ESB_NOTIF_VALID 1 +#define PSIHB_ESB_NOTIF_VALID PPC_BIT(63) #define PSIHB_IVT_OFFSET 0x70 #define PSIHB_IVT_OFF_SHIFT 32 /*