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Mon, 19 Jul 2021 13:20:50 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:20:50 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:49:20 +0530 Message-Id: <20210719132012.150948-10-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 8sv1sDaqAT43b7d0TG6BDFxTKJcdVSBp X-Proofpoint-ORIG-GUID: 8sv1sDaqAT43b7d0TG6BDFxTKJcdVSBp X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 mlxscore=0 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 09/61] psi/p10: Activate P10 interrupts X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Behave as P9 for now until we know more on P10. Interface should be the same, apart from the size of the ESB pages. Signed-off-by: Cédric Le Goater [Fixed suprious interrupt issue - Vasant] Signed-off-by: Vasant Hegde --- hw/psi.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++- include/psi.h | 7 ++++++ 2 files changed, 70 insertions(+), 1 deletion(-) diff --git a/hw/psi.c b/hw/psi.c index 545a81643..f95a066d3 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -266,7 +266,10 @@ static void psi_spurious_fsp_irq(struct psi *psi) prlog(PR_NOTICE, "PSI: Spurious interrupt, attempting clear\n"); - if (proc_gen == proc_gen_p9) { + if (proc_gen == proc_gen_p10) { + reg = PSIHB_XSCOM_P10_HBCSR_CLR; + bit = PSIHB_XSCOM_P10_HBSCR_FSP_IRQ; + } else if (proc_gen == proc_gen_p9) { reg = PSIHB_XSCOM_P9_HBCSR_CLR; bit = PSIHB_XSCOM_P9_HBSCR_FSP_IRQ; } else if (proc_gen == proc_gen_p8) { @@ -737,6 +740,61 @@ static void psi_init_p9_interrupts(struct psi *psi) out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); } +/* + * P9 and P10 have the same PSIHB interface + */ +static const struct irq_source_ops psi_p10_irq_ops = { + .interrupt = psihb_p9_interrupt, + .attributes = psi_p9_irq_attributes, + .name = psi_p9_irq_name, +}; + +static void psi_init_p10_interrupts(struct psi *psi) +{ + struct proc_chip *chip; + u64 val; + /* TODO (clg) : fix ESB page size to 64k when ready */ + uint32_t esb_shift = 12; + + /* Grab chip */ + chip = get_chip(psi->chip_id); + if (!chip) + return; + + /* Configure the CI BAR */ + phys_map_get(chip->id, PSIHB_ESB, 0, &val, NULL); + val |= PSIHB_ESB_CI_VALID; + out_be64(psi->regs + PSIHB_ESB_CI_BASE, val); + + val = in_be64(psi->regs + PSIHB_ESB_CI_BASE); + psi->esb_mmio = (void *)(val & ~PSIHB_ESB_CI_VALID); + prlog(PR_DEBUG, "PSI[0x%03x]: ESB MMIO at @%p\n", + psi->chip_id, psi->esb_mmio); + + /* Grab and configure the notification port */ + val = xive_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); + val |= PSIHB_ESB_NOTIF_VALID; + out_be64(psi->regs + PSIHB_ESB_NOTIF_ADDR, val); + + /* Setup interrupt offset */ + val = xive_get_notify_base(psi->interrupt); + val <<= 32; + out_be64(psi->regs + PSIHB_IVT_OFFSET, val); + + /* Register sources */ + prlog(PR_DEBUG, + "PSI[0x%03x]: Interrupts sources registered for P10 DD%i.%i\n", + psi->chip_id, 0xf & (chip->ec_level >> 4), chip->ec_level & 0xf); + + xive_register_hw_source(psi->interrupt, P9_PSI_NUM_IRQS, + esb_shift, psi->esb_mmio, XIVE_SRC_LSI, + psi, &psi_p10_irq_ops); + + /* Reset irq handling and switch to ESB mode */ + out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, PSIHB_IRQ_RESET); + out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); +} + static void psi_init_interrupts(struct psi *psi) { /* Configure the interrupt BUID and mask it */ @@ -747,6 +805,9 @@ static void psi_init_interrupts(struct psi *psi) case proc_gen_p9: psi_init_p9_interrupts(psi); break; + case proc_gen_p10: + psi_init_p10_interrupts(psi); + break; default: /* Unknown: just no interrupts */ prerror("PSI: Unknown interrupt type\n"); @@ -826,6 +887,7 @@ static void psi_create_mm_dtnode(struct psi *psi) "ibm,power8-psi"); break; case proc_gen_p9: + case proc_gen_p10: dt_add_property_strings(np, "compatible", "ibm,psi", "ibm,power9-psi"); psi_create_p9_int_map(psi, np); diff --git a/include/psi.h b/include/psi.h index f7b5927ca..a7104ef0b 100644 --- a/include/psi.h +++ b/include/psi.h @@ -116,6 +116,13 @@ #define PSIHB_XSCOM_P9_HBCSR_CLR 0x13 #define PSIHB_XSCOM_P9_HBSCR_FSP_IRQ PPC_BIT(17) +#define PSIHB_XSCOM_P10_BASE 0xa +#define PSIHB_XSCOM_P10_HBBAR_EN PPC_BIT(63) +#define PSIHB_XSCOM_P10_HBCSR 0xe +#define PSIHB_XSCOM_P10_HBCSR_SET 0x12 +#define PSIHB_XSCOM_P10_HBCSR_CLR 0x13 +#define PSIHB_XSCOM_P10_HBSCR_FSP_IRQ PPC_BIT(17) + /* P9 PSI Interrupts */ #define P9_PSI_IRQ_PSI 0 #define P9_PSI_IRQ_OCC 1