diff mbox series

[07/10] npu: move npu_set_fence_state() to phb_ops

Message ID 20210626023824.1124164-8-npiggin@gmail.com
State Superseded
Headers show
Series hwprobe patches | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (9d52c580d3fabbea6b276b98f925ab0fceebb96c)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Nicholas Piggin June 26, 2021, 2:38 a.m. UTC
From: Stewart Smith <stewart@flamingspork.com>

This lets us consider not building in npu.o

Signed-off-by: Stewart Smith <stewart@flamingspork.com>
---
 core/hmi.c    | 2 +-
 hw/npu.c      | 7 +++++--
 include/npu.h | 1 -
 include/pci.h | 3 +++
 4 files changed, 9 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/core/hmi.c b/core/hmi.c
index 120fe4b57..ee4c168e3 100644
--- a/core/hmi.c
+++ b/core/hmi.c
@@ -768,7 +768,7 @@  static void find_npu_checkstop_reason(int flat_chip_id,
 	      npu_fir_action0, npu_fir_action1);
 
 	/* Set the NPU to fenced since it can't recover. */
-	npu_set_fence_state(p, true);
+	phb->ops->set_fence_state(phb, true);
 
 	/* Set up the HMI event */
 	hmi_evt->severity = OpalHMI_SEV_WARNING;
diff --git a/hw/npu.c b/hw/npu.c
index 2b5364c33..6992e7e72 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -925,7 +925,9 @@  static int64_t npu_eeh_next_error(struct phb *phb,
 }
 
 /* For use in error injection and handling. */
-void npu_set_fence_state(struct npu *p, bool fence) {
+static void npu_set_fence_state(struct phb *phb, bool fence) {
+	struct npu *p = phb_to_npu(phb);
+
 	p->fenced = fence;
 
 	if (fence)
@@ -968,7 +970,7 @@  static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number,
 		return OPAL_PARAMETER;
 	} else if (type == 1) {
 		/* Emulate fence mode. */
-		npu_set_fence_state(p, true);
+		npu_set_fence_state(phb, true);
 	} else {
 		/* Cause a freeze with an invalid MMIO read.  If the BAR is not
 		 * enabled, this will checkstop the machine.
@@ -1012,6 +1014,7 @@  static const struct phb_ops npu_ops = {
 	.get_diag_data2		= NULL,
 	.set_capi_mode		= NULL,
 	.set_capp_recovery	= NULL,
+	.set_fence_state	= npu_set_fence_state,
 };
 
 static void assign_mmio_bars(uint32_t gcid, uint32_t xscom,
diff --git a/include/npu.h b/include/npu.h
index 50cc9c9fc..45818a28f 100644
--- a/include/npu.h
+++ b/include/npu.h
@@ -153,7 +153,6 @@  int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf,
 			  uint32_t offset, uint32_t len, uint32_t *data,
 			  bool write);
 
-void npu_set_fence_state(struct npu *p, bool fence);
 void npu_dev_procedure_reset(struct npu_dev *dev);
 
 #define NPUDBG(p, fmt, a...)	prlog(PR_DEBUG, "NPU%d: " fmt, \
diff --git a/include/pci.h b/include/pci.h
index eb23a6d9b..05d02171b 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -340,6 +340,9 @@  struct phb_ops {
 	/* Get/set PBCQ Tunnel BAR register */
 	void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr);
 	int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr);
+
+	/* Currently only used by NPU HMI code */
+	void (*set_fence_state)(struct phb *phb, bool fence);
 };
 
 enum phb_type {