From patchwork Thu Jun 4 13:21:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1303636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49dBsM6q8Rz9sPF for ; Fri, 5 Jun 2020 03:02:15 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49dBsM39qgzDqnv for ; Fri, 5 Jun 2020 03:02:15 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=46.105.56.76; helo=6.mo179.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 10802 seconds by postgrey-1.36 at bilbo; Fri, 05 Jun 2020 03:00:00 AEST Received: from 6.mo179.mail-out.ovh.net (6.mo179.mail-out.ovh.net [46.105.56.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49dBpn01sWzDqnk for ; Fri, 5 Jun 2020 02:59:59 +1000 (AEST) Received: from player739.ha.ovh.net (unknown [10.110.115.215]) by mo179.mail-out.ovh.net (Postfix) with ESMTP id 6785616C93A for ; Thu, 4 Jun 2020 15:21:53 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player739.ha.ovh.net (Postfix) with ESMTPSA id 0A4BFF02633D; Thu, 4 Jun 2020 13:21:49 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G00668ee0c84-fc45-4421-aa54-f466ef51d220, 2E0AA79A099E542C5FE1C9A79F210F9E9C727315) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2020 15:21:20 +0200 Message-Id: <20200604132126.750999-6-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200604132126.750999-1-clg@kaod.org> References: <20200604132126.750999-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17685917212856323033 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeguddgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejfeelrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH 05/11] xive/p9: Clarify the escalation IRQ encoding X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When an interrupt can not be delivered, an escalation interrupt can be triggered. The EQ descriptor of the pending interrupt should be configured to generate an escalation event, 'e' bit, and words 4 and 5 of the EQ descriptor should contain an IVE pointing to the escalation EQ to trigger. This is why EQs are considered as interrupt sources and registered as such when initializing the interrupt controller. These interrupts are identified as escalations by setting a special bit in their global interrupt number. Clarify that and check that the number of EQDs is not overflowing the global interrupt encoding. Signed-off-by: Cédric Le Goater Reviewed-by: Gustavo Romero --- hw/xive.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 2a132ce87f3b..4a029c3e97db 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -503,16 +503,21 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) * the top 8 bits are reserved for the CPPR value. */ #define INT_SHIFT 20 +#define INT_ESC_SHIFT (INT_SHIFT + 4) /* 4bits block id */ #if XIVE_INT_ORDER > INT_SHIFT #error "Too many ESBs for IRQ encoding" #endif +#if XIVE_EQ_ORDER > INT_SHIFT +#error "Too many EQs for escalation IRQ number encoding" +#endif + #define GIRQ_TO_BLK(__g) (((__g) >> INT_SHIFT) & 0xf) #define GIRQ_TO_IDX(__g) ((__g) & ((1 << INT_SHIFT) - 1)) #define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << INT_SHIFT | (__i)) -#define GIRQ_IS_ESCALATION(__g) ((__g) & 0x01000000) -#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | 0x01000000) +#define GIRQ_IS_ESCALATION(__g) ((__g) & (1 << INT_ESC_SHIFT)) +#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | (1 << INT_ESC_SHIFT)) /* Block/IRQ to chip# conversions */ #define PC_BLK_TO_CHIP(__b) (xive_block_to_chip[__b])