From patchwork Tue Apr 7 14:17:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1267444 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48xTzQ02nMz9sSc for ; Wed, 8 Apr 2020 00:18:41 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48xTzP3fZ8zDqf3 for ; Wed, 8 Apr 2020 00:18:41 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=hegdevasant@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48xTyz02xZzDqLK for ; Wed, 8 Apr 2020 00:18:18 +1000 (AEST) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 037E3FMR095892 for ; Tue, 7 Apr 2020 10:18:16 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 3082j8teub-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 07 Apr 2020 10:18:16 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 7 Apr 2020 15:17:53 +0100 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 037EIAjV44826792 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 7 Apr 2020 14:18:10 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 19427A405F; Tue, 7 Apr 2020 14:18:10 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 13A95A4062; Tue, 7 Apr 2020 14:18:09 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.79.180.90]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 7 Apr 2020 14:18:08 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Tue, 7 Apr 2020 19:47:34 +0530 X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20040714-0008-0000-0000-0000036C349F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20040714-0009-0000-0000-00004A8DCEA1 Message-Id: <20200407141734.1770-1-hegdevasant@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-07_06:2020-04-07, 2020-04-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 malwarescore=0 suspectscore=1 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004070123 Subject: [Skiboot] [PATCH] MPIPL: Add support to save crash CPU details on FSP system X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" OPAL uses different path to trigger MPIPL: - On BMC system we call SBE S0 interrupt - On FSP system we call `attn` instruction Currently on BMC system we collect crash CPU PIR details.. which is needed to generate proper dump. This happens just before calling SBE S0 interrupt. Since we don't use this path in FSP system OPAL is not saving crashing CPU details. Hence by default `opalcore` is not pointing to crashing CPU and not showing proper backtrace. We have to go through all CPUs to find crashing CPU backtrace. This patch move this function to common place so that if MPIPL is supported we collect crashing CPU data. Signed-off-by: Vasant Hegde --- core/opal-dump.c | 9 +++++++++ core/utils.c | 4 ++++ hw/sbe-p9.c | 3 --- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/core/opal-dump.c b/core/opal-dump.c index 639946c79..a31ecbe4d 100644 --- a/core/opal-dump.c +++ b/core/opal-dump.c @@ -487,6 +487,15 @@ static void post_mpipl_get_opal_data(void) void opal_mpipl_save_crashing_pir(void) { + struct dt_node *opal_node; + + opal_node = dt_find_by_path(dt_root, "ibm,opal"); + if (!opal_node) + return; + + if (!dt_find_by_path(opal_node, "dump")) + return; + mpipl_metadata->crashing_pir = this_cpu()->pir; prlog(PR_NOTICE, "Crashing PIR = 0x%x\n", this_cpu()->pir); } diff --git a/core/utils.c b/core/utils.c index 0d2f5e894..d778fcdff 100644 --- a/core/utils.c +++ b/core/utils.c @@ -12,6 +12,7 @@ #include #include #include +#include void __noreturn assert_fail(const char *msg, const char *file, unsigned int line, const char *function) @@ -33,6 +34,9 @@ void __noreturn assert_fail(const char *msg, const char *file, prlog(PR_EMERG, "assert failed at %s:%u: %s\n", file, line, msg); backtrace(); + /* Save crashing CPU details */ + opal_mpipl_save_crashing_pir(); + if (platform.terminate) platform.terminate(msg); diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index 31f8cb9c0..18caa0a28 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -958,9 +958,6 @@ void p9_sbe_terminate(void) return; } - /* Save crashing CPU details */ - opal_mpipl_save_crashing_pir(); - /* * Send S0 interrupt to all SBE. Sequence: * - S0 interrupt on secondary chip SBE