From patchwork Sat Mar 28 01:08:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 1263135 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48q0xb4Jt9z9sSJ for ; Sat, 28 Mar 2020 12:09:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48q0xb3xn6zDqTZ for ; Sat, 28 Mar 2020 12:09:39 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=bauerman@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48q0wq09F8zDqws for ; Sat, 28 Mar 2020 12:08:58 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 02S13AUC132702 for ; Fri, 27 Mar 2020 21:08:56 -0400 Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0b-001b2d01.pphosted.com with ESMTP id 2ywcj2ae17-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 27 Mar 2020 21:08:56 -0400 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 02S16WjY031350 for ; Sat, 28 Mar 2020 01:08:55 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma04wdc.us.ibm.com with ESMTP id 2ywaw9pg36-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 28 Mar 2020 01:08:55 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 02S18sYm42795348 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 28 Mar 2020 01:08:54 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6D59AC6059; Sat, 28 Mar 2020 01:08:54 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E6196C605B; Sat, 28 Mar 2020 01:08:51 +0000 (GMT) Received: from morokweng.localdomain.com (unknown [9.85.174.163]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Sat, 28 Mar 2020 01:08:50 +0000 (GMT) From: Thiago Jung Bauermann To: skiboot@lists.ozlabs.org Date: Fri, 27 Mar 2020 22:08:05 -0300 Message-Id: <20200328010806.20621-3-bauerman@linux.ibm.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200328010806.20621-1-bauerman@linux.ibm.com> References: <20200328010806.20621-1-bauerman@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.645 definitions=2020-03-27_09:2020-03-27, 2020-03-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 mlxscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=361 impostorscore=0 suspectscore=0 clxscore=1015 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2003280003 Subject: [Skiboot] [PATCH 2/3] SBE: Use the Ultravisor to interact with the SBE X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When an Ultravisor is present, access to XCOMs used to interact with the SBE are denied. To deal with that, the Ultravisor offers an UV_SEND_SBE_COMMAND ultracall which Skiboot can use to request some SBE operations to be performed by the Ultravisor on its behalf. We use it to set up the timer, to read the SBE doorbell register when receiving an interrupt from the SBE and for starting an MPIPL. Signed-off-by: Thiago Jung Bauermann --- hw/sbe-p9.c | 75 +++++++++++++++++++++++++++++++++++++++----- include/ultravisor.h | 20 ++++++++++++ 2 files changed, 88 insertions(+), 7 deletions(-) diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index 5ff44d545..bbe2f46d9 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -354,8 +354,17 @@ static void p9_sbe_process_queue(struct p9_sbe *sbe) while (!list_empty(&sbe->msg_list)) { msg = list_top(&sbe->msg_list, struct p9_sbe_msg, link); + /* Send message */ - rc = p9_sbe_msg_send(sbe, msg); + if (uv_present) { + /* This is the only message that we ever send. */ + assert(msg == timer_ctrl_msg); + + rc = uv_send_sbe_command(sbe->chip_id, SBE_CHIPOP_TIMER, + msg->reg[1], NULL); + } else + rc = p9_sbe_msg_send(sbe, msg); + if (rc == OPAL_SUCCESS) return; @@ -647,6 +656,36 @@ again: } } +/* + * Use the Ultravisor to learn what caused an SBE interrupt, and act + * accordingly. + * + * WARNING: This will drop sbe->lock + */ +static void p9_uv_handle_sbe_interrupt(struct p9_sbe *sbe) +{ + uint64_t doorbell; + int rc; + + do { + rc = uv_send_sbe_command(sbe->chip_id, + SBE_CHIPOP_HANDLE_INTERRUPT, 0, + &doorbell); + + if (doorbell & SBE_HOST_RESET) + p9_sbe_after_reset(sbe); + + if (doorbell & SBE_HOST_MSG_READ) + p9_sbe_send_complete(sbe); + + if (doorbell & SBE_HOST_PASSTHROUGH) + prd_sbe_passthrough(sbe->chip_id); + + if (doorbell & SBE_HOST_TIMER_EXPIRY) + p9_sbe_timer_response(sbe); + } while (rc == 0 && doorbell != 0); +} + void p9_sbe_interrupt(uint32_t chip_id) { struct proc_chip *chip; @@ -658,8 +697,14 @@ void p9_sbe_interrupt(uint32_t chip_id) sbe = chip->sbe; lock(&sbe->lock); - __p9_sbe_interrupt(sbe); + + if (uv_present) + p9_uv_handle_sbe_interrupt(sbe); + else + __p9_sbe_interrupt(sbe); + p9_sbe_process_queue(sbe); + unlock(&sbe->lock); } @@ -708,7 +753,11 @@ static void p9_sbe_timeout_poll_one(struct p9_sbe *sbe) * possible that SBE has responded, but OPAL didn't act on that. * Hence check for SBE response. */ - __p9_sbe_interrupt(sbe); + if (uv_present) + p9_uv_handle_sbe_interrupt(sbe); + else + __p9_sbe_interrupt(sbe); + p9_sbe_timer_poll(sbe); if (list_empty(&sbe->msg_list)) @@ -948,6 +997,20 @@ void p9_sbe_init(void) opal_add_poller(p9_sbe_timeout_poll, NULL); } +static int p9_sbe_start_mpipl(u64 chip_id) +{ + int rc; + + if (uv_present) + rc = uv_send_sbe_command(chip_id, SBE_CHIPOP_START_MPIPL, + 0, NULL); + else + rc = xscom_write(chip_id, SBE_CONTROL_REG_RW, + SBE_CONTROL_REG_S0); + + return rc; +} + /* Terminate and initiate MPIPL */ void p9_sbe_terminate(void) { @@ -980,8 +1043,7 @@ void p9_sbe_terminate(void) continue; } - rc = xscom_write(chip->id, - SBE_CONTROL_REG_RW, SBE_CONTROL_REG_S0); + rc = p9_sbe_start_mpipl(chip->id); /* Initiate normal reboot */ if (rc) { prlog(PR_ERR, "Failed to write S0 interrupt [chip id = %x]\n", @@ -996,8 +1058,7 @@ void p9_sbe_terminate(void) return; } - rc = xscom_write(primary_chip, - SBE_CONTROL_REG_RW, SBE_CONTROL_REG_S0); + rc = p9_sbe_start_mpipl(primary_chip); if (rc) { prlog(PR_ERR, "Failed to write S0 interrupt [chip id = %x]\n", primary_chip); diff --git a/include/ultravisor.h b/include/ultravisor.h index 347b085d7..eb855687c 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -14,8 +14,15 @@ #define UCALL_BUFSIZE 4 #define UV_READ_SCOM 0xF114 #define UV_WRITE_SCOM 0xF118 +#define UV_SEND_SBE_COMMAND 0xF150 #define UV_FDT_MAX_SIZE 0x100000 +enum sbe_chipop_ops { + SBE_CHIPOP_TIMER, + SBE_CHIPOP_HANDLE_INTERRUPT, + SBE_CHIPOP_START_MPIPL, +}; + extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); extern int start_uv(uint64_t entry, void *fdt); extern bool uv_present; @@ -41,4 +48,17 @@ static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) return ucall(UV_WRITE_SCOM, retbuf, partid, pcb_addr, val); } +static inline int uv_send_sbe_command(u64 chip_id, enum sbe_chipop_ops opcode, + u64 input, u64 *output) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + int rc; + + rc = ucall(UV_SEND_SBE_COMMAND, retbuf, chip_id, opcode, input); + if (output) + *output = retbuf[0]; + + return rc; +} + #endif /* __ULTRAVISOR_H */