diff mbox series

[RFC,v4,06/16] Add memcons support for ultravisor

Message ID 20200227122042.32692-7-grimm@linux.ibm.com
State Superseded
Headers show
Series Ultravisor support in skiboot | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (82aed17a5468aff6b600ee1694a10a60f942c018)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Ryan Grimm Feb. 27, 2020, 12:20 p.m. UTC 
From: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>

The ultravisor console buffer is provided at offset 0x01100000 from the
skiboot base.

Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Santosh Sivaraj <santosh@fossix.org>
---
 hw/ultravisor.c            | 13 +++++++++++++
 include/console.h          |  3 +++
 include/debug_descriptor.h |  1 +
 include/mem-map.h          | 16 ++++++++++------
 4 files changed, 27 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/hw/ultravisor.c b/hw/ultravisor.c
index 2fc1ecf1..a2fe63cc 100644
--- a/hw/ultravisor.c
+++ b/hw/ultravisor.c
@@ -8,10 +8,20 @@ 
 #include <processor.h>
 #include <opal-api.h>
 #include <cpu.h>
+#include <debug_descriptor.h>
+#include <console.h>
 
 static struct dt_node *uv_fw_node;
 static uint64_t uv_base_addr;
 
+struct memcons uv_memcons __section(".data.memcons") = {
+	.magic		= MEMCONS_MAGIC,
+	.obuf_phys	= INMEM_UV_CON_START,
+	.ibuf_phys	= INMEM_UV_CON_START + INMEM_UV_CON_OUT_LEN,
+	.obuf_size	= INMEM_UV_CON_OUT_LEN,
+	.ibuf_size	= INMEM_UV_CON_IN_LEN,
+};
+
 static void cpu_start_ultravisor(void *fdt)
 {
 	uint64_t uv_entry = 0;
@@ -83,4 +93,7 @@  void init_uv()
 							uv_base_addr, uv_dt_src);
 
 	memcpy((void *)uv_base_addr, (void *)uv_dt_src, UV_LOAD_MAX_SIZE);
+
+	dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons);
+	debug_descriptor.uv_memcons_phys = (u64)&uv_memcons;
 }
diff --git a/include/console.h b/include/console.h
index 61448e28..1e7c2a10 100644
--- a/include/console.h
+++ b/include/console.h
@@ -28,9 +28,12 @@  struct memcons {
 };
 
 extern struct memcons memcons;
+extern struct memcons uv_memcons;
 
 #define INMEM_CON_IN_LEN	16
 #define INMEM_CON_OUT_LEN	(INMEM_CON_LEN - INMEM_CON_IN_LEN)
+#define INMEM_UV_CON_IN_LEN	16
+#define INMEM_UV_CON_OUT_LEN	(INMEM_UV_CON_LEN - INMEM_UV_CON_IN_LEN)
 
 /* Console driver */
 struct con_ops {
diff --git a/include/debug_descriptor.h b/include/debug_descriptor.h
index cbe9293e..949e3d92 100644
--- a/include/debug_descriptor.h
+++ b/include/debug_descriptor.h
@@ -20,6 +20,7 @@  struct debug_descriptor {
 
 	/* Memory console */
 	__be64	memcons_phys;
+	__be64	uv_memcons_phys;
 	__be32	memcons_tce;
 	__be32	memcons_obuf_tce;
 	__be32	memcons_ibuf_tce;
diff --git a/include/mem-map.h b/include/mem-map.h
index 8ac11e91..3686b92c 100644
--- a/include/mem-map.h
+++ b/include/mem-map.h
@@ -91,16 +91,20 @@ 
 #define INMEM_CON_START		(SKIBOOT_BASE + 0x01000000)
 #define INMEM_CON_LEN  		0x100000
 
-/* This is the location of HBRT console buffer at base + 17M */
-#define HBRT_CON_START		(SKIBOOT_BASE + 0x01100000)
+/* This is the location of our ultravisor console buffer at base + 17M */
+#define INMEM_UV_CON_START	(SKIBOOT_BASE + 0x01100000)
+#define INMEM_UV_CON_LEN	0x100000
+
+/* This is the location of HBRT console buffer at base + 18M */
+#define HBRT_CON_START		(SKIBOOT_BASE + 0x01200000)
 #define HBRT_CON_LEN  		0x100000
 
-/* Tell FSP to put the init data at base + 20M, allocate 8M */
-#define SPIRA_HEAP_BASE		(SKIBOOT_BASE + 0x01200000)
+/* Tell FSP to put the init data at base + 19M, allocate 8M */
+#define SPIRA_HEAP_BASE		(SKIBOOT_BASE + 0x01300000)
 #define SPIRA_HEAP_SIZE		0x00800000
 
 /* This is our PSI TCE table. It's 256K entries on P8 */
-#define PSI_TCE_TABLE_BASE	(SKIBOOT_BASE + 0x01a00000)
+#define PSI_TCE_TABLE_BASE	(SKIBOOT_BASE + 0x01c00000)
 #define PSI_TCE_TABLE_SIZE	0x00200000UL
 
 /* This is our dump result table after MPIPL. Hostboot will write to this
@@ -119,7 +123,7 @@ 
  *
  * (Ensure this has at least a 64k alignment)
  */
-#define SKIBOOT_SIZE		0x01c10000
+#define SKIBOOT_SIZE		0x01e00000
 
 /* We start laying out the CPU stacks from here, indexed by PIR
  * each stack is STACK_SIZE in size (naturally aligned power of