From patchwork Wed Feb 26 18:34:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1245275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SPjc0PyNz9sPR for ; Thu, 27 Feb 2020 05:39:48 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=DAnsjG/s; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48SPjb3GRwzDqmh for ; Thu, 27 Feb 2020 05:39:47 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::1043; helo=mail-pj1-x1043.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=DAnsjG/s; dkim-atps=neutral Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48SPhb6W3MzDqVR for ; Thu, 27 Feb 2020 05:38:55 +1100 (AEDT) Received: by mail-pj1-x1043.google.com with SMTP id q39so27259pjc.0 for ; Wed, 26 Feb 2020 10:38:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nu2oCsdKa+eYnZibEOXw9SxOBh+9KKSkfdp4kmz6W+w=; b=DAnsjG/s6/ljh85X0CYiLsUnu94rmQpgV+2acob4wCoe6QjEbAg4O8O50KBFk8Vjuq JaC1pThOUzF/Ahd+IK/mdoDNffYruo1QF8BLQc4gbKIG5Ae3OwSbt//fHO5TiCD4+4ki 2mdX87FQ/gRBtnwXQsNqRLevFV/lEFRvKMSKTakH9HUWXoU+lBxQnH9+7nPiSil7sMW2 HIACedtf2ClMBIgZi3iQFkryedLiaP/kp9OgNgVdyAyR7PZeNLRsiicqZkkM7Ofoter7 w31YD6trBCAO0vl97YMMT3BzZai0DJs1xiZYHQ7fJlFRX9G+F2bEVM4xWOUnZT78NZxj duUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nu2oCsdKa+eYnZibEOXw9SxOBh+9KKSkfdp4kmz6W+w=; b=mNt71CFhQOq+6wgQzN557pLjFuKkpnCGi3ZFQG1L1HSjfAZSu9jgCKRS1xjyrVVKxh W32J9gGSwRlpZvtS/LMRVrZJwOWU4DncitEv1fffjYenMvY2SkKJS/ZxqZSpq1tFgq0R cJRYfGTbBRhosRrvkboAyxQ/wngFp61WSVMJB5yb3kaauuru2ZcB+Nqak+rpywPakFTJ DPuT3Rt+zL9ETxDAcutYCF4RxPQ+C6quXYC3xXGHNwRwJ9vno5qLHmcGInK/ZOYBpoS5 QYZ11EtS0SRz7GHfLB02XEQeCMuRdUFk2d2/+lr8+J4gIpa7QGzUFYWMt/LKuDzfyg+2 ju0g== X-Gm-Message-State: APjAAAVZuDPRWD4YprenI/ofPoYvRe9aw9gSlqIw4U1aW3JUp6ZgXM6A 1Ccc5UtutjEDZabqSccrUrCtb0GC X-Google-Smtp-Source: APXvYqzk12svawwvSUn/K9QnqXHltUcQKe0S96cbQWbZftX8D/2Qce2NdrhQgrK4c9pd3bMW9ppdKA== X-Received: by 2002:a17:90a:33a1:: with SMTP id n30mr470667pjb.6.1582742332510; Wed, 26 Feb 2020 10:38:52 -0800 (PST) Received: from bobo.ibm.com ([61.68.187.74]) by smtp.gmail.com with ESMTPSA id v8sm3715247pfn.172.2020.02.26.10.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 10:38:51 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 27 Feb 2020 04:34:01 +1000 Message-Id: <20200226183408.1626737-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200226183408.1626737-1-npiggin@gmail.com> References: <20200226183408.1626737-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 2/9] move the __this_cpu register to r16, reserve r13-r15 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There have been several bugs between Linux and OPAL caused by both using r13 for their primary per-CPU data address. This patch moves OPAL to use r16 for this, and prevents the compiler from touching r13-r15 (r14,r15 allow Linux to use additional fixed registers in future). This helps code to be a little more robust, and may make crashes in OPAL (or debugging with pdbg or in simulators) easier to debug by having easy access to the PACA. Later, if we allow interrupts (other than non-maskable) to be taken when running in skiboot, Linux's interrupt return handler does not restore r13 if the interrupt was taken in PR=0 state, which would corrupt the skiboot r13 register, so this allows for the possibility, although it will have to become a formal OPAL ABI requirement if we rely on it. Signed-off-by: Nicholas Piggin --- Makefile.main | 11 +++++++++-- asm/head.S | 36 ++++++++++++++++++------------------ asm/misc.S | 8 ++++---- include/cpu.h | 2 +- 4 files changed, 32 insertions(+), 25 deletions(-) diff --git a/Makefile.main b/Makefile.main index daca012be..f0213a312 100644 --- a/Makefile.main +++ b/Makefile.main @@ -96,7 +96,14 @@ endif CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables CFLAGS += -mcpu=power8 CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb -CFLAGS += $(call try-cflag,$(CC),-ffixed-r13) +# r13,r14,r15 are preserved for OS to use as fixed registers. +# These could be saved and restored in and out of skiboot, but it's more +# robust to avoid touching them. +CFLAGS += -ffixed-r13 +CFLAGS += -ffixed-r14 +CFLAGS += -ffixed-r15 +# r16 is skiboot's per-CPU data pointer. +CFLAGS += -ffixed-r16 CFLAGS += $(call try-cflag,$(CC),-std=gnu11) ifeq ($(LITTLE_ENDIAN),1) @@ -127,7 +134,7 @@ endif # Check if the new parametrized stack protector option is supported # by gcc, otherwise disable stack protector -STACK_PROT_CFLAGS := -mstack-protector-guard=tls -mstack-protector-guard-reg=r13 +STACK_PROT_CFLAGS := -mstack-protector-guard=tls -mstack-protector-guard-reg=r16 STACK_PROT_CFLAGS += -mstack-protector-guard-offset=0 HAS_STACK_PROT := $(call test_cflag,$(CC),$(STACK_PROT_CFLAGS)) diff --git a/asm/head.S b/asm/head.S index 0b4b1a5f0..143f8af53 100644 --- a/asm/head.S +++ b/asm/head.S @@ -25,7 +25,7 @@ addi stack_reg,stack_reg,EMERGENCY_CPU_STACKS_OFFSET@l; #define GET_CPU() \ - clrrdi %r13,%r1,STACK_SHIFT + clrrdi %r16,%r1,STACK_SHIFT #define SAVE_GPR(reg,sp) std %r##reg,STACK_GPR##reg(sp) #define REST_GPR(reg,sp) ld %r##reg,STACK_GPR##reg(sp) @@ -403,7 +403,7 @@ boot_entry: * before relocation so we need to keep track of its location to wake * them up. */ - mr %r15,%r30 + mr %r18,%r30 /* Check if we need to copy ourselves up and update %r30 to * be our new offset @@ -449,7 +449,7 @@ boot_entry: /* Tell secondaries to move to second stage (relocated) spin loop */ LOAD_IMM32(%r3, boot_flag - __head) - add %r3,%r3,%r15 + add %r3,%r3,%r18 li %r0,1 stw %r0,0(%r3) @@ -464,18 +464,18 @@ boot_entry: addi %r3,%r3,8 bdnz 1b - /* Get our per-cpu pointer into r13 */ + /* Get our per-cpu pointer into r16 */ GET_CPU() #ifdef STACK_CHECK_ENABLED /* Initialize stack bottom mark to 0, it will be updated in C code */ li %r0,0 - std %r0,CPUTHREAD_STACK_BOT_MARK(%r13) + std %r0,CPUTHREAD_STACK_BOT_MARK(%r16) #endif /* Initialize the stack guard */ LOAD_IMM64(%r3,STACK_CHECK_GUARD_BASE); xor %r3,%r3,%r31 - std %r3,0(%r13) + std %r3,0(%r16) /* Jump to C */ mr %r3,%r27 @@ -536,7 +536,7 @@ secondary_not_found: b . call_relocate: - mflr %r14 + mflr %r17 LOAD_IMM32(%r4,__dynamic_start - __head) LOAD_IMM32(%r5,__rela_dyn_start - __head) add %r4,%r4,%r30 @@ -545,7 +545,7 @@ call_relocate: bl relocate cmpwi %r3,0 bne 1f - mtlr %r14 + mtlr %r17 blr 1: /* Fatal relocate failure */ attn @@ -592,12 +592,12 @@ reset_wakeup: /* Get PIR */ mfspr %r31,SPR_PIR - /* Get that CPU stack base and use it to restore r13 */ + /* Get that CPU stack base and use it to restore r16 */ GET_STACK(%r1,%r31) GET_CPU() /* Restore original stack pointer */ - ld %r1,CPUTHREAD_SAVE_R1(%r13) + ld %r1,CPUTHREAD_SAVE_R1(%r16) /* Restore more stuff */ lwz %r4,STACK_CR(%r1) @@ -655,7 +655,7 @@ reset_fast_reboot_wakeup: /* Get PIR */ mfspr %r31,SPR_PIR - /* Get that CPU stack base and use it to restore r13 */ + /* Get that CPU stack base and use it to restore r16 */ GET_STACK(%r1,%r31) GET_CPU() @@ -923,17 +923,17 @@ opal_entry: std %r9,STACK_GPR9(%r1) std %r10,STACK_GPR10(%r1) - /* Save Token (r0), LR and r13 */ + /* Save Token (r0), LR and r16 */ mflr %r12 std %r0,STACK_GPR0(%r1) - std %r13,STACK_GPR13(%r1) + std %r16,STACK_GPR16(%r1) std %r12,STACK_LR(%r1) /* Get the CPU thread */ GET_CPU() /* Store token in CPU thread */ - std %r0,CPUTHREAD_CUR_TOKEN(%r13) + std %r0,CPUTHREAD_CUR_TOKEN(%r16) /* Mark the stack frame */ li %r12,STACK_ENTRY_OPAL_API @@ -975,14 +975,14 @@ opal_entry: bl opal_exit_check /* r3 is preserved */ /* - * Restore r1 and r13 before decrementing in_opal_call. - * Move per-cpu pointer to volatile r12, restore lr, r1, r13. + * Restore r1 and r16 before decrementing in_opal_call. + * Move per-cpu pointer to volatile r12, restore lr, r1, r16. */ .Lreturn: ld %r12,STACK_LR(%r1) mtlr %r12 - mr %r12,%r13 - ld %r13,STACK_GPR13(%r1) + mr %r12,%r16 + ld %r16,STACK_GPR16(%r1) ld %r1,STACK_GPR1(%r1) .Lreject: sync /* release barrier vs quiescing */ diff --git a/asm/misc.S b/asm/misc.S index 647f60b26..9904b806f 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -213,7 +213,7 @@ enter_p8_pm_state: bl pm_save_regs /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) + std %r1,CPUTHREAD_SAVE_R1(%r16) /* Winkle or nap ? */ cmpli %cr0,0,%r3,0 @@ -221,7 +221,7 @@ enter_p8_pm_state: /* nap sequence */ ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) +0: ld %r0,CPUTHREAD_SAVE_R1(%r16) cmpd cr0,%r0,%r0 bne 0b PPC_INST_NAP @@ -229,7 +229,7 @@ enter_p8_pm_state: /* rvwinkle sequence */ 1: ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) +0: ld %r0,CPUTHREAD_SAVE_R1(%r16) cmpd cr0,%r0,%r0 bne 0b PPC_INST_RVWINKLE @@ -250,7 +250,7 @@ enter_p9_pm_state: bl pm_save_regs /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) + std %r1,CPUTHREAD_SAVE_R1(%r16) mtspr SPR_PSSCR,%r3 PPC_INST_STOP diff --git a/include/cpu.h b/include/cpu.h index 686310d71..9b7f41dfb 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -212,7 +212,7 @@ extern u8 get_available_nr_cores_in_chip(u32 chip_id); core = next_available_core_in_chip(core, chip_id)) /* Return the caller CPU (only after init_cpu_threads) */ -register struct cpu_thread *__this_cpu asm("r13"); +register struct cpu_thread *__this_cpu asm("r16"); static inline __nomcount struct cpu_thread *this_cpu(void) { return __this_cpu;