From patchwork Thu Sep 5 03:08:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1158185 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46P5K375h2z9s3Z for ; Thu, 5 Sep 2019 13:09:59 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="u2vD+eKt"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46P5K369s2zDql0 for ; Thu, 5 Sep 2019 13:09:59 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::442; helo=mail-pf1-x442.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="u2vD+eKt"; dkim-atps=neutral Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46P5Hz4X0qzDqRm for ; Thu, 5 Sep 2019 13:09:03 +1000 (AEST) Received: by mail-pf1-x442.google.com with SMTP id h195so753819pfe.5 for ; Wed, 04 Sep 2019 20:09:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6rpWUTIPTWhgxWvCrnHwQjhdP4BRSI6kiF25LX+WfNE=; b=u2vD+eKtM2sDkCtnc61btORV6Z1d7ZR1SN6auOQsvCwisXhYEQdwMboJ9kXlwvcwp7 bOpNh+q6j2lwqRqsClGGtginiluRlUyl1KR07+j0FzVT/cL9ftVU/b/oMGhwlWnrT/bM lf8/NrtBaNHEOgbU9W0wtPD8pQQh+R0UUKm/98Zt2xl+5NIDpSvsaRJ78NlPizFIQ662 51Msgdxhbe7I330manq+RP4FKmzGDAiAqzK9zH/KsBLDJc+A3ojLWen4cn38+y/Ggrp9 FO/ROLGieW+oWwEtQIlZX5nyxJGJr/kZSJ0MLBTXm4b3XnE2NNBRwbkR5HgIEEwPQS6r veRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6rpWUTIPTWhgxWvCrnHwQjhdP4BRSI6kiF25LX+WfNE=; b=SpsdKNMNw5utnfkedb2kS2yhRDX3BKoDWZuPe/U2nhBfaGyQEe0yRyW9OoAzN2bXO3 5NnXgNRKVIfBmK3+p+jsu7LLnB+sg4jFgcbBxO29vZcZOPez8G6bCOPy2XNA5fOdTosq UckqpNYRn1HhjWsuRQ6RAZMlb1QSc8MQfTSR6PMVAyu8CSXHcSzc/uziaBQ8JrbPGnVj +nj+nujcfmN+2X6/POc3VhxGrMSrWy+fP+2TyVLUOqpkBM/3/O7fQtBHyonrRXIkKMCG 7mVzZ65dMYRlixJMVEpCOfcPwmAJM+cjqrV/YPZUMytXqK10X295pu5ZCEJVBk5NV5yO mvZQ== X-Gm-Message-State: APjAAAXnnXiqjvx/QjcVub/2u3xAlfVmnWagK1Sb2bHDVLasqHIz67rp GES//KBDpppPJIZ7ypyhHH8zYGja X-Google-Smtp-Source: APXvYqzXY4/yYN4zEmFhtz3KAoCu/cCvXPScdDQSB073rXe+feyLpIfzp9pSIKUqttWwkFDcNq9goQ== X-Received: by 2002:aa7:83d1:: with SMTP id j17mr1111073pfn.35.1567652940829; Wed, 04 Sep 2019 20:09:00 -0700 (PDT) Received: from wafer.ozlabs.ibm.com.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id p189sm545844pfp.163.2019.09.04.20.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 20:09:00 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 5 Sep 2019 13:08:43 +1000 Message-Id: <20190905030845.15540-3-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190905030845.15540-1-oohall@gmail.com> References: <20190905030845.15540-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v2 3/5] hw/psi-p9: Mask OPAL-owned LSIs without handlers X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Some versions of Swift have the TPM interrupt line of the second chip pulled up instead of down. This causes the PSI's external (TPM) interrupt to constantly re-fire since it's an LSI and the interrupt signal is constantly active. There's nothing that can be done to clear the underlying interrupt condition so we to ensure that it's masked. The problem isn't really specific to the external interrupt and will occur for any of the PSI interrupts that don't have an actual handler (FSP, global error, and sometimes the external). When one of these is delivered to OPAL we should log that it happened and mask it to prevent re-firing. Cc: Cédric Le Goater Signed-off-by: Oliver O'Halloran Reviewed-by: Cédric Le Goater --- v2: Use __xive_source_mask() to mask the interrupt rather than opencoding the ESB manipulation in the PSI driver. look up the interrupt name from the name array rather than using the name callback. --- hw/psi.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index 99ec06ac488a..6c28eb0447ad 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -536,6 +536,29 @@ static char *psi_p9_irq_name(struct irq_source *is, uint32_t isn) return strdup(p9_psi_int_names[idx]); } +static void psi_p9_mask_unhandled_irq(struct irq_source *is, uint32_t isn) +{ + int idx = isn - psi->interrupt; + struct psi *psi = is->data; + const char *name; + + if (idx < ARRAY_SIZE(p9_psi_int_names)) + name = p9_psi_int_names[idx]; + else + name = "unknown irq"; + + prerror("PSI: Masking unhandled LSI %s (idx: %d)!\n", name, idx); + + /* + * All the PSI interrupts are LSIs and will be constantly re-fired + * unless the underlying interrupt condition is cleared. If we don't + * have a handler for the interrupt then it needs to be masked to + * prevent the IRQ from locking up the thread which handles it. + */ + __xive_source_mask(is, isn); + +} + static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) { struct psi *psi = is->data; @@ -548,21 +571,17 @@ static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) case P9_PSI_IRQ_OCC: occ_p9_interrupt(psi->chip_id); break; - case P9_PSI_IRQ_FSI: - printf("PSI: FSI irq received\n"); - break; case P9_PSI_IRQ_LPCHC: lpc_interrupt(psi->chip_id); break; case P9_PSI_IRQ_LOCAL_ERR: prd_psi_interrupt(psi->chip_id); break; - case P9_PSI_IRQ_GLOBAL_ERR: - printf("PSI: Global error irq received\n"); - break; case P9_PSI_IRQ_EXTERNAL: if (platform.external_irq) platform.external_irq(psi->chip_id); + else + psi_p9_mask_unhandled_irq(is, isn); break; case P9_PSI_IRQ_LPC_SIRQ0: case P9_PSI_IRQ_LPC_SIRQ1: @@ -580,6 +599,9 @@ static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) case P9_PSI_IRQ_PSU: p9_sbe_interrupt(psi->chip_id); break; + + default: + psi_p9_mask_unhandled_irq(is, isn); } } @@ -614,6 +636,7 @@ static const struct irq_source_ops psi_p9_irq_ops = { .interrupt = psihb_p9_interrupt, .attributes = psi_p9_irq_attributes, .name = psi_p9_irq_name, + .mask = psi_p9_mask_unhandled_irq, }; void psi_set_external_irq_policy(bool policy)