| Message ID | 20190604125712.6209-1-ilya@yadro.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Allow to create slot for downstream port of any switch | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch master (9cae036fafea468219892406a846639f2715854d) |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot | fail | Test snowpatch/job/snowpatch-skiboot on branch master |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco | success | Signed-off-by present |
On Tue, Jun 4, 2019 at 10:58 PM Ilya Kuznetsov <ilya@yadro.com> wrote: > > System vendor may build systems with large PCIe tree with > deeper switch topologies. Currenlty downstream ports slot > creation is limited to one switch. Patch allows to use more > by removing comparison to third parent. > > Signed-off-by: Ilya Kuznetsov <ilya@yadro.com> > --- > core/pcie-slot.c | 8 ++------ > 1 file changed, 2 insertions(+), 6 deletions(-) > > diff --git a/core/pcie-slot.c b/core/pcie-slot.c > index e7013d1e..b12e0fb2 100644 > --- a/core/pcie-slot.c > +++ b/core/pcie-slot.c > @@ -544,13 +544,9 @@ struct pci_slot *pcie_slot_create_dynamic(struct phb *phb, > if (!phb || !pd || pd->slot) > return NULL; > > - /* Try to create slot whose details aren't provided by platform. > - * We only care the downstream ports of PCIe switch that connects > - * to root port. > - */ > + /* Try to create slot whose details aren't provided by platform. */ > if (pd->dev_type != PCIE_TYPE_SWITCH_DNPORT || > - !pd->parent || !pd->parent->parent || > - pd->parent->parent->parent) > + !pd->parent || !pd->parent->parent) > return NULL; I'm not entirely sure why it had that restriction in the first place. We could probably just limit the check to: if (pd->dev_type != PCIE_TYPE_SWITCH_DNPORT) return NULL; The same function verifies the port has hotplug support advertised, so there's no real harm in allowing it. > ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false); > -- > 2.21.0 > > _______________________________________________ > Skiboot mailing list > Skiboot@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/skiboot
diff --git a/core/pcie-slot.c b/core/pcie-slot.c index e7013d1e..b12e0fb2 100644 --- a/core/pcie-slot.c +++ b/core/pcie-slot.c @@ -544,13 +544,9 @@ struct pci_slot *pcie_slot_create_dynamic(struct phb *phb, if (!phb || !pd || pd->slot) return NULL; - /* Try to create slot whose details aren't provided by platform. - * We only care the downstream ports of PCIe switch that connects - * to root port. - */ + /* Try to create slot whose details aren't provided by platform. */ if (pd->dev_type != PCIE_TYPE_SWITCH_DNPORT || - !pd->parent || !pd->parent->parent || - pd->parent->parent->parent) + !pd->parent || !pd->parent->parent) return NULL; ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
System vendor may build systems with large PCIe tree with deeper switch topologies. Currenlty downstream ports slot creation is limited to one switch. Patch allows to use more by removing comparison to third parent. Signed-off-by: Ilya Kuznetsov <ilya@yadro.com> --- core/pcie-slot.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)