From patchwork Wed Apr 3 09:08:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1075624 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Z0dq4XYhz9sS3 for ; Wed, 3 Apr 2019 20:09:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nIjiFQeR"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Z0dq2szGzDqQX for ; Wed, 3 Apr 2019 20:09:51 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::643; helo=mail-pl1-x643.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nIjiFQeR"; dkim-atps=neutral Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Z0dc59MfzDqFK for ; Wed, 3 Apr 2019 20:09:39 +1100 (AEDT) Received: by mail-pl1-x643.google.com with SMTP id ck15so6524445plb.3 for ; Wed, 03 Apr 2019 02:09:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XV9wTmrmmxHAlZxRxX0gnqCXXbBkxx3LCdVXnUZ2WFs=; b=nIjiFQeRckKxFzLMZqbgew7QOSrjXCbMbkRH5Ervzm4QGvjVFlcHzGM4NXkuVps5IQ +W3oUmcrNBuTpsw84fQrRaG6AkjraiNJ+2tNjLWaP5HGSQhNvpu3tXw0dJ/KHqVvcZbO nL92U+XEArWvgdqpK3z9QxXRnorgA4ciE1IemF3/6tH0LostQ1tCMDx1sPns4gnff05r 4lsFCNoYi2fwZDR8De1Z9s2PLzQLeWfJiHuk7C/C9gblzbgonV4uNzHzDQe3aMQHVLNY 8ry5sE9wy5JFMAVsFPyiVcOIBViTr9XhYhmh2C3fq+tMxIp7+479UeJjbDVK7uFtTI4E Iu6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XV9wTmrmmxHAlZxRxX0gnqCXXbBkxx3LCdVXnUZ2WFs=; b=IC5NxEJsCnyAezO/EtE1KLF9q2mDyKCnFZXIuMg1E6GQV1Qgdh+x/fuhd9iCL6UOtx rbsPRqhtOoj3aUk8dE/zS0LBhqtyLARpuBalJKJ9KrakcAnlW0yM1kdGuU6FM0C96+aM bmLEcS6Z40pvoz+3ZZK+oZK/pjTv0qJfiYVN3o0ZT4Db/kSWJzIfRGnE5dXxPdrnT1eA BqTUReXpUYWuxcIHbNE5IJ6HmT8H224VqKvsuL+m+/OUk2HlA7QLwKaXCwVoGPqSf80g TaZo7PsdwVamK3YDYZaluyytu2vxyHm99filARXzypwAaiOcn710EA7efi9r9ZmuEuz9 071w== X-Gm-Message-State: APjAAAUol3J3x/fmvoVMHXuR03xkSEIR0oft2NG0DUw2Ri5jInqXuesU aZnM4mexDxPhTJP+nN5EmdmMkLIB X-Google-Smtp-Source: APXvYqyKGgqcsAuH/byH4hWomZgvWDuYpzdEmTJdgD02hZfRzlRiisLfIJR1Csog7IkztdXhT+cbvA== X-Received: by 2002:a17:902:e109:: with SMTP id cc9mr23141427plb.148.1554282577036; Wed, 03 Apr 2019 02:09:37 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id t64sm39165764pfa.86.2019.04.03.02.09.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 02:09:36 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 3 Apr 2019 20:08:58 +1100 Message-Id: <20190403090920.362-2-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403090920.362-1-oohall@gmail.com> References: <20190403090920.362-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 01/23] platform/firenze-pci: Remove freset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The pci slot set_power_state() method is being converted to use a polling based API rather than async completion callbacks. This patch removes the firenze-pci freset method and the associated i2c competion callback since keeping them complicates the rework and they're going to be deleted later anyway. The set_power_state and get_power_state methods are retained and marked __unused since they will be reworked in a later patch. Signed-off-by: Oliver O'Halloran --- platforms/ibm-fsp/firenze-pci.c | 272 +------------------------------- 1 file changed, 4 insertions(+), 268 deletions(-) diff --git a/platforms/ibm-fsp/firenze-pci.c b/platforms/ibm-fsp/firenze-pci.c index ac2580fb4a9a..0ed53301485e 100644 --- a/platforms/ibm-fsp/firenze-pci.c +++ b/platforms/ibm-fsp/firenze-pci.c @@ -360,268 +360,7 @@ bail: firenze_inv_cnt = 0; } -/* The function is called when the I2C request is completed - * successfully, or with errors. - */ -static void firenze_i2c_req_done(int rc, struct i2c_request *req) -{ - struct pci_slot *slot = req->user_data; - uint32_t state; - - /* Check if there are errors for the completion */ - if (rc) { - /** - * @fwts-label FirenzePCII2CError - * @fwts-advice On Firenze platforms, I2C is used to control - * power to PCI slots. Errors here mean we may be in trouble - * in regards to PCI slot power on/off. - */ - prlog(PR_ERR, "Error %d from I2C request on slot %016llx\n", - rc, slot->id); - return; - } - - /* Check the request type */ - if (req->op != SMBUS_READ && req->op != SMBUS_WRITE) { - /** - * @fwts-label FirenzePCII2CInvalid - * @fwts-advice Likely a coding error: invalid I2C request. - */ - prlog(PR_ERR, "Invalid I2C request %d on slot %016llx\n", - req->op, slot->id); - return; - } - - /* After writting power status to I2C slave, we need at least - * 5ms delay for the slave to settle down. We also have the - * delay after reading the power status as well. - */ - switch (slot->state) { - case FIRENZE_PCI_SLOT_FRESET_WAIT_RSP: - prlog(PR_DEBUG, "%016llx FRESET: I2C request completed\n", - slot->id); - state = FIRENZE_PCI_SLOT_FRESET_DELAY; - break; - case FIRENZE_PCI_SLOT_SPOWER_START: - prlog(PR_DEBUG, "%016llx SPOWER: I2C request completed\n", - slot->id); - state = FIRENZE_PCI_SLOT_SPOWER_DONE; - break; - default: - /** - * @fwts-label FirenzePCISlotI2CStateError - * @fwts-advice The Firenze platform uses I2C to control - * power to PCI slots. Something went wrong in the state - * machine controlling that. Slots may/may not have power. - */ - prlog(PR_ERR, "Wrong state %08x on slot %016llx\n", - slot->state, slot->id); - return; - } - - /* Switch to net state */ - pci_slot_set_state(slot, state); -} - -/* This function is called to setup normal PCI device or PHB slot. - * For the later case, the slot doesn't have the associated PCI - * device. Besides, the I2C response timeout is set to 5s. We might - * improve I2C in future to support priorized requests so that the - * timeout can be shortened. - */ -static int64_t firenze_pci_slot_freset(struct pci_slot *slot) -{ - struct firenze_pci_slot *plat_slot = slot->data; - uint8_t *pval, presence = 1; - uint32_t timeout; - - switch (slot->state) { - case FIRENZE_PCI_SLOT_NORMAL: - case FIRENZE_PCI_SLOT_FRESET_START: - prlog(PR_DEBUG, "%016llx FRESET: Starts\n", - slot->id); - - /* Bail if nothing is connected */ - if (slot->ops.get_presence_state) - slot->ops.get_presence_state(slot, &presence); - if (!presence) { - prlog(PR_DEBUG, "%016llx FRESET: No device\n", - slot->id); - return OPAL_SUCCESS; - } - - /* Prepare link down */ - if (slot->ops.prepare_link_change) { - prlog(PR_DEBUG, "%016llx FRESET: Prepares link down\n", - slot->id); - slot->ops.prepare_link_change(slot, false); - } - - /* Send I2C request */ - prlog(PR_DEBUG, "%016llx FRESET: Check power state\n", - slot->id); - plat_slot->next_state = - FIRENZE_PCI_SLOT_FRESET_POWER_STATE; - plat_slot->req->op = SMBUS_READ; - slot->retries = FIRENZE_PCI_SLOT_RETRIES; - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_FRESET_WAIT_RSP); - if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP)) - plat_slot->req->timeout = FIRENZE_PCI_I2C_TIMEOUT; - else - plat_slot->req->timeout = 0ul; - i2c_queue_req(plat_slot->req); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_WAIT_RSP: - if (slot->retries-- == 0) { - prlog(PR_DEBUG, "%016llx FRESET: Timeout waiting for %08x\n", - slot->id, plat_slot->next_state); - goto out; - } - - check_timers(false); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_DELAY: - prlog(PR_DEBUG, "%016llx FRESET: Delay %dms on I2C completion\n", - slot->id, FIRENZE_PCI_SLOT_DELAY); - pci_slot_set_state(slot, plat_slot->next_state); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_POWER_STATE: - /* Update last power status */ - pval = (uint8_t *)(plat_slot->req->rw_buf); - *plat_slot->power_status = *pval; - - /* Power is on, turn it off */ - if (((*pval) & plat_slot->power_mask) == plat_slot->power_on) { - prlog(PR_DEBUG, "%016llx FRESET: Power (%02x) on, turn off\n", - slot->id, *pval); - (*pval) &= ~plat_slot->power_mask; - (*pval) |= plat_slot->power_off; - plat_slot->req->op = SMBUS_WRITE; - slot->retries = FIRENZE_PCI_SLOT_RETRIES; - plat_slot->next_state = - FIRENZE_PCI_SLOT_FRESET_POWER_OFF; - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_FRESET_WAIT_RSP); - - if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP)) - timeout = FIRENZE_PCI_I2C_TIMEOUT; - else - timeout = 0ul; - plat_slot->req->timeout = timeout; - - i2c_queue_req(plat_slot->req); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - } - - /* Power is off, turn it on */ - /* Fallthrough */ - case FIRENZE_PCI_SLOT_FRESET_POWER_OFF: - /* Update last power status */ - pval = (uint8_t *)(plat_slot->req->rw_buf); - *plat_slot->power_status = *pval; - - prlog(PR_DEBUG, "%016llx FRESET: Power (%02x) off, turn on\n", - slot->id, *pval); - (*pval) &= ~plat_slot->power_mask; - (*pval) |= plat_slot->power_on; - plat_slot->req->op = SMBUS_WRITE; - plat_slot->next_state = - FIRENZE_PCI_SLOT_FRESET_POWER_ON; - slot->retries = FIRENZE_PCI_SLOT_RETRIES; - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_FRESET_WAIT_RSP); - - if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP)) - plat_slot->req->timeout = FIRENZE_PCI_I2C_TIMEOUT; - else - plat_slot->req->timeout = 0ul; - i2c_queue_req(plat_slot->req); - return pci_slot_set_sm_timeout(slot, - msecs_to_tb(FIRENZE_PCI_SLOT_DELAY)); - case FIRENZE_PCI_SLOT_FRESET_POWER_ON: - /* Update last power status */ - pval = (uint8_t *)(plat_slot->req->rw_buf); - *plat_slot->power_status = *pval; - - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_LINK_START); - return slot->ops.poll_link(slot); - default: - prlog(PR_DEBUG, "%016llx FRESET: Unexpected state %08x\n", - slot->id, slot->state); - } - -out: - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_NORMAL); - return OPAL_HARDWARE; -} - -static int64_t firenze_pci_slot_perst(struct pci_slot *slot) -{ - struct firenze_pci_slot *plat_slot = slot->data; - uint8_t presence = 1; - uint16_t ctrl; - - switch (slot->state) { - case FIRENZE_PCI_SLOT_NORMAL: - case FIRENZE_PCI_SLOT_FRESET_START: - prlog(PR_DEBUG, "%016llx PERST: Starts\n", - slot->id); - - /* Bail if nothing is connected */ - if (slot->ops.get_presence_state) - slot->ops.get_presence_state(slot, &presence); - if (!presence) { - prlog(PR_DEBUG, "%016llx PERST: No device\n", - slot->id); - return OPAL_SUCCESS; - } - - /* Prepare link down */ - if (slot->ops.prepare_link_change) { - prlog(PR_DEBUG, "%016llx PERST: Prepare link down\n", - slot->id); - slot->ops.prepare_link_change(slot, false); - } - - /* Assert PERST */ - prlog(PR_DEBUG, "%016llx PERST: Assert\n", - slot->id); - pci_cfg_read16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, &ctrl); - ctrl |= plat_slot->perst_bit; - pci_cfg_write16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, ctrl); - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_PERST_DEASSERT); - return pci_slot_set_sm_timeout(slot, msecs_to_tb(250)); - case FIRENZE_PCI_SLOT_PERST_DEASSERT: - /* Deassert PERST */ - pci_cfg_read16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, &ctrl); - ctrl &= ~plat_slot->perst_bit; - pci_cfg_write16(slot->phb, slot->pd->bdfn, - plat_slot->perst_reg, ctrl); - pci_slot_set_state(slot, - FIRENZE_PCI_SLOT_PERST_DELAY); - return pci_slot_set_sm_timeout(slot, msecs_to_tb(1500)); - case FIRENZE_PCI_SLOT_PERST_DELAY: - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_LINK_START); - return slot->ops.poll_link(slot); - default: - prlog(PR_DEBUG, "%016llx PERST: Unexpected state %08x\n", - slot->id, slot->state); - } - - pci_slot_set_state(slot, FIRENZE_PCI_SLOT_NORMAL); - return OPAL_HARDWARE; -} - -static int64_t firenze_pci_slot_get_power_state(struct pci_slot *slot, +static int64_t __unused firenze_pci_slot_get_power_state(struct pci_slot *slot, uint8_t *val) { if (slot->state != FIRENZE_PCI_SLOT_NORMAL) @@ -640,7 +379,7 @@ static int64_t firenze_pci_slot_get_power_state(struct pci_slot *slot, return OPAL_SUCCESS; } -static int64_t firenze_pci_slot_set_power_state(struct pci_slot *slot, +static int64_t __unused firenze_pci_slot_set_power_state(struct pci_slot *slot, uint8_t val) { struct firenze_pci_slot *plat_slot = slot->data; @@ -835,7 +574,6 @@ static void firenze_pci_setup_power_mgt(struct pci_slot *slot, plat_slot->req->offset_bytes = 1; plat_slot->req->rw_buf = plat_slot->i2c_rw_buf; plat_slot->req->rw_len = 1; - plat_slot->req->completion = firenze_i2c_req_done; plat_slot->req->user_data = slot; plat_slot->req->bus = plat_slot->i2c_bus; @@ -907,9 +645,7 @@ static void firenze_pci_slot_init(struct pci_slot *slot) * configuration after we have a blocking API for that. */ if (plat_slot->req) { - slot->ops.freset = firenze_pci_slot_freset; - slot->ops.get_power_state = firenze_pci_slot_get_power_state; - slot->ops.set_power_state = firenze_pci_slot_set_power_state; + /* placeholder */ prlog(PR_DEBUG, "%016llx: External power mgt initialized\n", slot->id); } else if (info->inband_perst) { @@ -927,7 +663,7 @@ static void firenze_pci_slot_init(struct pci_slot *slot) case 0x874810b5: /* PLX8748 */ plat_slot->perst_reg = 0x80; plat_slot->perst_bit = 0x0400; - slot->ops.freset = firenze_pci_slot_perst; + /* placeholder */ break; } }