diff mbox series

[v2,1/5] skiboot/doc: Add documentation for trace-mode in imc.rst

Message ID 20181212061545.9756-2-anju@linux.vnet.ibm.com
State Changes Requested
Headers show
Series skiboot: OPAL support for IMC trace-mode | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success master/apply_patch Successfully applied
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master

Commit Message

Anju T Sudhakar Dec. 12, 2018, 6:15 a.m. UTC
Add documentation for IMC trace-mode in imc.rst.

Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
---
 doc/imc.rst | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Stewart Smith Feb. 25, 2019, 3:57 a.m. UTC | #1
Anju T Sudhakar <anju@linux.vnet.ibm.com> writes:
> Add documentation for IMC trace-mode in imc.rst.
>
> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
> ---
>  doc/imc.rst | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/doc/imc.rst b/doc/imc.rst
> index 3324aa36..40d262f0 100644
> --- a/doc/imc.rst
> +++ b/doc/imc.rst
> @@ -44,6 +44,15 @@ sampling duration) fetches the counter data and accumulate to main memory.
>  Memory to accumulate counter data are refered from "PDBAR" (per-core scom)
>  and "LDBAR" per-thread spr.
>
> +Trace mode of IMC:
> +------------------
> +
> +POWER9 support two modes for IMC which are the Accumulation mode and
> +Trace mode. In IMC Trace mode, event counted is fixed for cycles and on
> +each overflow, hardware snapshots the program counter along with other
> +details and writes into memory pointed by LDBAR. LDBAR has bits to
> +indicate the IMC trace-mode.
> +

I'm having trouble parsing what's being said here.

I can't understand what "event counted is fixed for cycles" means, nor
what overflow is being referred to.

This needs to be reworded so it's clear as to what's going on and what
the trace mode means and does.
Anju T Sudhakar March 5, 2019, 5:40 a.m. UTC | #2
Hi Stewart,

Thank you for reviewing the patch.

On 2/25/19 9:27 AM, Stewart Smith wrote:
> Anju T Sudhakar <anju@linux.vnet.ibm.com> writes:
>> Add documentation for IMC trace-mode in imc.rst.
>>
>> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
>> ---
>>   doc/imc.rst | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/doc/imc.rst b/doc/imc.rst
>> index 3324aa36..40d262f0 100644
>> --- a/doc/imc.rst
>> +++ b/doc/imc.rst
>> @@ -44,6 +44,15 @@ sampling duration) fetches the counter data and accumulate to main memory.
>>   Memory to accumulate counter data are refered from "PDBAR" (per-core scom)
>>   and "LDBAR" per-thread spr.
>>
>> +Trace mode of IMC:
>> +------------------
>> +
>> +POWER9 support two modes for IMC which are the Accumulation mode and
>> +Trace mode. In IMC Trace mode, event counted is fixed for cycles and on
>> +each overflow, hardware snapshots the program counter along with other
>> +details and writes into memory pointed by LDBAR. LDBAR has bits to
>> +indicate the IMC trace-mode.
>> +
> I'm having trouble parsing what's being said here.
>
> I can't understand what "event counted is fixed for cycles" means, nor
> what overflow is being referred to.

So here, the event which we are counting is `cycles`, and for the time 
being

this event is fixed. Also we are writing a 64 bit value to(trace-scom 
value) to trace-imc

address. This value has a field called 'cpmc_load' (which is mentioned 
in the

subsequent patch), and when the cpmc counter overflows the data captured

is written to the memory.

> This needs to be reworded so it's clear as to what's going on and what
> the trace mode means and does.
>

Sure. I will brief this in a better way.


Thanks,

Anju
diff mbox series

Patch

diff --git a/doc/imc.rst b/doc/imc.rst
index 3324aa36..40d262f0 100644
--- a/doc/imc.rst
+++ b/doc/imc.rst
@@ -44,6 +44,15 @@  sampling duration) fetches the counter data and accumulate to main memory.
 Memory to accumulate counter data are refered from "PDBAR" (per-core scom)
 and "LDBAR" per-thread spr.
 
+Trace mode of IMC:
+------------------
+
+POWER9 support two modes for IMC which are the Accumulation mode and
+Trace mode. In IMC Trace mode, event counted is fixed for cycles and on
+each overflow, hardware snapshots the program counter along with other
+details and writes into memory pointed by LDBAR. LDBAR has bits to
+indicate the IMC trace-mode.
+
 OPAL APIs:
 ----------