From patchwork Fri Nov 16 01:04:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rashmica Gupta X-Patchwork-Id: 998646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42x0Pg3xHyz9sB5 for ; Fri, 16 Nov 2018 12:04:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="t5cEEERM"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42x0Pg29v5zF3hJ for ; Fri, 16 Nov 2018 12:04:39 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="t5cEEERM"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=rashmica.g@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="t5cEEERM"; dkim-atps=neutral Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42x0PX0gXXzF3R5 for ; Fri, 16 Nov 2018 12:04:31 +1100 (AEDT) Received: by mail-pg1-x541.google.com with SMTP id z11so7169385pgu.0 for ; Thu, 15 Nov 2018 17:04:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=dj+pGOE8p8n6d0nliM85rqB3iNJE7kZ93F4YR04g8gI=; b=t5cEEERM9+SzqvwxmzGYnYs0i424PR63xEa6eGok8BYEzSnYMMwFHgsqpiA47VERtU spqwmCgjAOGWDA8qUIlTVERuYqYGI2VIYRCEVDzIi/PMxaUxToYndnAcMCd+lRFHJEry mtcu5pijK7fyH6OoehYE21inLjh5NTczC09POOrc262ILdad5MQGPnV2AydR02p4TW5S CBwi+oJE0PaTdK0F8s+xKcc/aD46AizdDjdb5wouIE0xNrs5094q+TSjngKEpVuGGPXt VUOw0M3Q7TyvL2a6m5KOe6QcptHcB50pPwysZf+h0usY84ya9bdjf3ObxWcE6LEFsURu uKzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=dj+pGOE8p8n6d0nliM85rqB3iNJE7kZ93F4YR04g8gI=; b=ey35ogtE6kb4NoLfpqp8JO+fL/xwPsAqbE6Fq/edn4NRLBHQCBdLEvUk4rejmE419X ehr74kNAi0XQ+TjSTzpJIKAk4xeXMPqpuRv7fVav/paqtJI8lpDUbx26mUjKXHm7f+DC HrjvDNRjcIwFqt1oVTXpvmj0KfdSOeDa5u38bhtzXMD3P/5+5UnoFCi9keHEPzTLTzqB BbDYyAvCO8K0Z+rKcbN2cfmgXvtA9avceavhZcyfeSmdSxalXD9saA9MdZOIsODpajLE mzLUQ2g9mgCYye0bi9icTcny7CzQ2JOijKZKUPYu7ba+wiFM537Fxs3N2K5OdPrxKgdX +HdA== X-Gm-Message-State: AGRZ1gIvbfVIITulCGLH+oGzejrtbBTG6yLML6qVSKmqTOM3VM4ygmtm HNkR0E9R3I+Sngs9EXXj5I3zz9gJ X-Google-Smtp-Source: AJdET5f2zeJ61snaOQB+wjneu1PwNdhm91E/xl+39lzliOxvj8gIMwnb5/rFlOW3P8tu3whJlbd0tQ== X-Received: by 2002:a62:2545:: with SMTP id l66-v6mr8891337pfl.207.1542330269951; Thu, 15 Nov 2018 17:04:29 -0800 (PST) Received: from rashmica.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id m12-v6sm35121331pff.173.2018.11.15.17.04.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 15 Nov 2018 17:04:29 -0800 (PST) From: Rashmica Gupta To: skiboot@lists.ozlabs.org, aik@ozlabs.ru Date: Fri, 16 Nov 2018 12:04:16 +1100 Message-Id: <20181116010416.18357-1-rashmica.g@gmail.com> X-Mailer: git-send-email 2.17.2 Subject: [Skiboot] [PATCH] Add the other 7 ATSD registers to the device tree. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Suggested-by: Alexey Kardashevskiy Signed-off-by: Rashmica Gupta --- hw/npu2.c | 15 ++++++++++----- include/npu2-regs.h | 2 ++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/npu2.c b/hw/npu2.c index d7d94357..28745682 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -1781,7 +1781,7 @@ static void npu2_add_phb_properties(struct npu2 *p) { struct dt_node *np = p->phb_nvlink.dt_node; uint32_t icsp = get_ics_phandle(); - uint64_t mm_base, mm_size, mmio_atsd; + uint64_t mm_base, mm_size; /* * Add various properties that HB doesn't have to @@ -1803,10 +1803,15 @@ static void npu2_add_phb_properties(struct npu2 *p) dt_add_property_cells(np, "ibm,opal-reserved-pe", NPU2_RESERVED_PE_NUM); - mmio_atsd = (u64) p->regs + - NPU2_REG_OFFSET(NPU2_STACK_ATSD, NPU2_BLOCK_ATSD0, NPU2_XTS_MMIO_ATSD_LAUNCH); - dt_add_property_cells(np, "ibm,mmio-atsd", hi32(mmio_atsd), - lo32(mmio_atsd)); + dt_add_property_cells(np, "ibm,mmio-atsd", + hi32(MMIO_ATSD_ADDR(p->regs, 0)), lo32(MMIO_ATSD_ADDR(p->regs, 0)), + hi32(MMIO_ATSD_ADDR(p->regs, 1)), lo32(MMIO_ATSD_ADDR(p->regs, 1)), + hi32(MMIO_ATSD_ADDR(p->regs, 2)), lo32(MMIO_ATSD_ADDR(p->regs, 2)), + hi32(MMIO_ATSD_ADDR(p->regs, 3)), lo32(MMIO_ATSD_ADDR(p->regs, 3)), + hi32(MMIO_ATSD_ADDR(p->regs, 4)), lo32(MMIO_ATSD_ADDR(p->regs, 4)), + hi32(MMIO_ATSD_ADDR(p->regs, 5)), lo32(MMIO_ATSD_ADDR(p->regs, 5)), + hi32(MMIO_ATSD_ADDR(p->regs, 6)), lo32(MMIO_ATSD_ADDR(p->regs, 6)), + hi32(MMIO_ATSD_ADDR(p->regs, 7)), lo32(MMIO_ATSD_ADDR(p->regs, 7))); /* * Memory window is exposed as 64-bits non-prefetchable diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 8c1ba5ff..165e0b79 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -579,6 +579,8 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_XTS_MMIO_ATSD_LAUNCH 0x000 #define NPU2_XTS_MMIO_ATSD_AVA 0x008 #define NPU2_XTS_MMIO_ATSD_STATUS 0x010 +#define MMIO_ATSD_ADDR(p, n) (u64) p + NPU2_REG_OFFSET(NPU2_STACK_ATSD,\ + NPU2_BLOCK_ATSD##n, NPU2_XTS_MMIO_ATSD_LAUNCH) /* ALTD SCOM addresses */ #define NPU2_MISC_SCOM_IND_SCOM_ADDR 0x68e