| Message ID | 20171206225638.23479-1-mikey@neuling.org |
|---|---|
| State | Accepted |
| Headers | show |
| Series | phb4: Change PCI MMIO timers | expand |
Michael Neuling <mikey@neuling.org> writes: > Currently we have a mismatch between the NCU and PCI timers for MMIO > accesses. The PCI timers must be lower than the NCU timers otherwise > it may cause checkstops. > > This changes PCI timeouts controlled by skiboot to 33-50ms. It should > be forwards and backwards compatible with expected hostboot changes to > the NCU timer. > > Signed-off-by: Michael Neuling <mikey@neuling.org> > --- > hw/phb4.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) thanks, merged to master as of 5cee066746d238feef51dd7b0359c3456b089748 Something for 5.9.x or not?
Stewart Smith <stewart@linux.vnet.ibm.com> writes: > Michael Neuling <mikey@neuling.org> writes: >> Currently we have a mismatch between the NCU and PCI timers for MMIO >> accesses. The PCI timers must be lower than the NCU timers otherwise >> it may cause checkstops. >> >> This changes PCI timeouts controlled by skiboot to 33-50ms. It should >> be forwards and backwards compatible with expected hostboot changes to >> the NCU timer. >> >> Signed-off-by: Michael Neuling <mikey@neuling.org> >> --- >> hw/phb4.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) > > thanks, merged to master as of 5cee066746d238feef51dd7b0359c3456b089748 > > Something for 5.9.x or not? aaaand the results of the off-list discussion was that yes, this is wanted in 5.9.x, so merged to 5.9.x as of 58fe47833c86ea7101aa8d57d71a78f383c269c6
diff --git a/hw/phb4.c b/hw/phb4.c index c8539c24fd..6c59462bd6 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -4509,13 +4509,13 @@ static void phb4_init_hw(struct phb4 *p, bool first_init) out_be64(p->regs + PHB_TCE_SPEC_CTL, 0x0000000000000000ull); /* Init_133 - Timeout Control Register 1 */ - out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x0018150000160000ull); + out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x0015150000150000ull); /* Init_134 - Timeout Control Register 2 */ out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x0000181700000000ull); /* Init_135 - PBL Timeout Control Register */ - out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL, 0x2015000000000000ull); + out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL, 0x2013000000000000ull); /* Mark the PHB as functional which enables all the various sequences */ p->state = PHB4_STATE_FUNCTIONAL;
Currently we have a mismatch between the NCU and PCI timers for MMIO accesses. The PCI timers must be lower than the NCU timers otherwise it may cause checkstops. This changes PCI timeouts controlled by skiboot to 33-50ms. It should be forwards and backwards compatible with expected hostboot changes to the NCU timer. Signed-off-by: Michael Neuling <mikey@neuling.org> --- hw/phb4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)