@@ -810,13 +810,22 @@ init_replicated_sprs:
4: /* P9 */
/* LPCR: sane value */
LOAD_IMM64(%r3,0x0040000000000000)
+ isync
mtspr SPR_LPCR, %r3
sync
isync
+ /* Zero out MMU registers */
+ li %r3,0
+ ptesync
+ mtspr SPR_PTCR,%r3
+ isync
+ mtspr SPR_LPID,%r3
+ isync
+ mtspr SPR_PID,%r3
+ isync
/* DSCR: Stride-N Stream Enable */
LOAD_IMM64(%r3,0x0000000000000010)
mtspr SPR_DSCR,%r3
-
9: blr
.global enter_nap
@@ -53,6 +53,7 @@
#define SPR_SRR1 0x01b /* RW: Exception save/restore reg 1 */
#define SPR_CFAR 0x01c /* RW: Come From Address Register */
#define SPR_AMR 0x01d /* RW: Authority Mask Register */
+#define SPR_PID 0x030 /* RW: Process ID */
#define SPR_IAMR 0x03d /* RW: Instruction Authority Mask Register */
#define SPR_RPR 0x0ba /* RW: Relative Priority Register */
#define SPR_TBRL 0x10c /* RO: Timebase low */
@@ -75,9 +76,11 @@
#define SPR_HSRR1 0x13b /* RW: HV Exception save/restore reg 1 */
#define SPR_TFMR 0x13d
#define SPR_LPCR 0x13e
+#define SPR_LPID 0x13f /* RW: Logical Partition Identifier */
#define SPR_HMER 0x150 /* Hypervisor Maintenance Exception */
#define SPR_HMEER 0x151 /* HMER interrupt enable mask */
#define SPR_AMOR 0x15d
+#define SPR_PTCR 0x1d0 /* RW: Partition table control Register */
#define SPR_PSSCR 0x357 /* RW: Stop status and control (ISA 3) */
#define SPR_TSCR 0x399
#define SPR_HID0 0x3f0
When fast-rebooting, secondaries are sreset into OPAL with their MMU registers (PTCR, PID, etc) still set up by the host OS. Clear them at fastr-reboot time, before loading a new kernel. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- asm/head.S | 11 ++++++++++- include/processor.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-)