| Message ID | 20171020115942.26732-6-mikey@neuling.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/9] phb4: Update comment | expand |
On Fri, 2017-10-20 at 22:59 +1100, Michael Neuling wrote: > PHB fatal error recovery needs MMIO enabled otherwise the PHB will > freeze the PE once the driver starts accessing the device again. I don't understand the patch and how it relates to the above changelog. You seem to be forcing any write to the PCI command register to set those 2 bits. It feels to me like the real problem might be in the callers ... How come are those 2 bits cleared and not restored properly by Linux ? > Signed-off-by: Michael Neuling <mikey@neuling.org> > --- > hw/phb4.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/phb4.c b/hw/phb4.c > index 0170e43a89..0841136cc7 100644 > --- a/hw/phb4.c > +++ b/hw/phb4.c > @@ -421,7 +421,7 @@ static int64_t phb4_rc_write(struct phb4 *p, uint32_t offset, uint8_t sz, > break; > default: > /* Workaround PHB config space enable */ > - if ((p->rev == PHB4_REV_NIMBUS_DD10) && (reg == PCI_CFG_CMD)) > + if (reg == PCI_CFG_CMD) > val |= PCI_CFG_CMD_MEM_EN | PCI_CFG_CMD_BUS_MASTER_EN; > PHBLOGCFG(p, "000 CFG%02d Wr %02x=%08x\n", 8 * sz, reg, val); > if (use_asb)
On Fri, 2017-10-20 at 14:56 +0200, Benjamin Herrenschmidt wrote: > On Fri, 2017-10-20 at 22:59 +1100, Michael Neuling wrote: > > PHB fatal error recovery needs MMIO enabled otherwise the PHB will > > freeze the PE once the driver starts accessing the device again. > > I don't understand the patch and how it relates to the above changelog. > > You seem to be forcing any write to the PCI command register to set > those 2 bits. It feels to me like the real problem might be in the > callers ... How come are those 2 bits cleared and not restored > properly by Linux ? I agree, I do feel like I'm papering over another problem. I don't remember why we had to do this original patch on DD1. The commit message doesn't explain it either and I don't know why kexec would change between DD1 and DD2. /me shakes fist at past mikey. commit 2d4f3cf4bcfa7cfd6e4dddb0ca5a4cbaedc27a15 Author: Michael Neuling <mikey@neuling.org> Date: Wed Nov 16 16:49:24 2016 +1100 phb4: Fix config space enable bits on DD1 Fix enabling config space on DD1. Without this PCI devices disappear on kexec. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Mikey > > > Signed-off-by: Michael Neuling <mikey@neuling.org> > > --- > > hw/phb4.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/hw/phb4.c b/hw/phb4.c > > index 0170e43a89..0841136cc7 100644 > > --- a/hw/phb4.c > > +++ b/hw/phb4.c > > @@ -421,7 +421,7 @@ static int64_t phb4_rc_write(struct phb4 *p, uint32_t > > offset, uint8_t sz, > > break; > > default: > > /* Workaround PHB config space enable */ > > - if ((p->rev == PHB4_REV_NIMBUS_DD10) && (reg == > > PCI_CFG_CMD)) > > + if (reg == PCI_CFG_CMD) > > val |= PCI_CFG_CMD_MEM_EN | > > PCI_CFG_CMD_BUS_MASTER_EN; > > PHBLOGCFG(p, "000 CFG%02d Wr %02x=%08x\n", 8 * sz, reg, > > val); > > if (use_asb) > >
diff --git a/hw/phb4.c b/hw/phb4.c index 0170e43a89..0841136cc7 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -421,7 +421,7 @@ static int64_t phb4_rc_write(struct phb4 *p, uint32_t offset, uint8_t sz, break; default: /* Workaround PHB config space enable */ - if ((p->rev == PHB4_REV_NIMBUS_DD10) && (reg == PCI_CFG_CMD)) + if (reg == PCI_CFG_CMD) val |= PCI_CFG_CMD_MEM_EN | PCI_CFG_CMD_BUS_MASTER_EN; PHBLOGCFG(p, "000 CFG%02d Wr %02x=%08x\n", 8 * sz, reg, val); if (use_asb)
PHB fatal error recovery needs MMIO enabled otherwise the PHB will freeze the PE once the driver starts accessing the device again. Signed-off-by: Michael Neuling <mikey@neuling.org> --- hw/phb4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)