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[06/13] xive: Spread the notification ports a bit

Message ID 20170116043635.25849-6-benh@kernel.crashing.org
State Accepted
Headers show

Commit Message

Benjamin Herrenschmidt Jan. 16, 2017, 4:36 a.m. UTC 
There are 4 snoopers, 0 and 3 are pretty busy, so let's use a mix
of 1 and 2 for the PHB and PSI notification ports. We do that by
using different cache line offsets. We use 1 for PHB0 which tends
to be the highest performance one and 2 for everybody else

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 hw/xive.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)
diff mbox

Patch

diff --git a/hw/xive.c b/hw/xive.c
index 6908835..33695f0 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -2043,28 +2043,30 @@  uint64_t xive_get_notify_port(uint32_t chip_id, uint32_t ent)
 	 * PH4_2  addr        0x110        (CL 2 DW2)
 	 * etc.
 	 * >>
+	 *
+	 * I'm using snoop1 for PHB0 and snoop2 for everybody else.
 	 */
 	switch(ent) {
 	case XIVE_HW_SRC_PHBn(0):
 		offset = 0x100;
 		break;
 	case XIVE_HW_SRC_PHBn(1):
-		offset = 0x108;
+		offset = 0x208;
 		break;
 	case XIVE_HW_SRC_PHBn(2):
-		offset = 0x110;
+		offset = 0x210;
 		break;
 	case XIVE_HW_SRC_PHBn(3):
-		offset = 0x118;
+		offset = 0x218;
 		break;
 	case XIVE_HW_SRC_PHBn(4):
-		offset = 0x120;
+		offset = 0x220;
 		break;
 	case XIVE_HW_SRC_PHBn(5):
-		offset = 0x128;
+		offset = 0x228;
 		break;
 	case XIVE_HW_SRC_PSI:
-		offset = 0x130;
+		offset = 0x230;
 		break;
 	default:
 		assert(false);