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[56/60] xive: Fix memory barrier in opal_xive_get_xirr()

Message ID 20161222031708.18752-56-benh@kernel.crashing.org
State Accepted
Headers show

Commit Message

Benjamin Herrenschmidt Dec. 22, 2016, 3:17 a.m. UTC 
We can do the Ack cycle using a simple load but we need a sync
before we look at the EQs, otherwise we might be missing the
EQ update corresponding to a priority in the ACK cycle.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 hw/xive.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
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Patch

diff --git a/hw/xive.c b/hw/xive.c
index acfcea4..4cf971d 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -3029,9 +3029,10 @@  static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll)
 
 	/* Perform the HV Ack cycle */
 	if (just_poll)
-		ack = in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS) >> 48;
+		ack = __in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS) >> 48;
 	else
-		ack = in_be16(xs->tm_ring1 + TM_SPC_ACK_HV_REG);
+		ack = __in_be16(xs->tm_ring1 + TM_SPC_ACK_HV_REG);
+	sync();
 	xive_cpu_vdbg(c, "get_xirr,%s=%04x\n", just_poll ? "POLL" : "ACK", ack);
 
 	/* Capture the old CPPR which we will return with the interrupt */