@@ -697,6 +697,14 @@ static bool tfmr_recover_non_tb_errors(uint64_t tfmr)
tfmr_reset_errors |= SPR_TFMR_HDEC_PARITY_ERROR;
}
+ if (tfmr & SPR_TFMR_DEC_PARITY_ERR) {
+ /* Set DEC with all ones */
+ mtspr(SPR_DEC, ~0);
+
+ /* set bit 59 to clear TFMR DEC parity error. */
+ tfmr_reset_errors |= SPR_TFMR_DEC_PARITY_ERR;
+ }
+
/* Write TFMR twice to clear the error */
mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
@@ -848,7 +856,8 @@ int chiptod_recover_tb_errors(void)
/*
* Now that TB is running, check for TFMR non-TB errors.
*/
- if (tfmr & SPR_TFMR_HDEC_PARITY_ERROR) {
+ if ((tfmr & SPR_TFMR_HDEC_PARITY_ERROR) ||
+ (tfmr & SPR_TFMR_DEC_PARITY_ERR)) {
if (!tfmr_recover_non_tb_errors(tfmr)) {
rc = 0;
goto error_out;
@@ -47,6 +47,7 @@
/* SPR register definitions */
#define SPR_DSISR 0x012 /* RW: Data storage interrupt status reg */
#define SPR_DAR 0x013 /* RW: Data address reg */
+#define SPR_DEC 0x016 /* RW: Decrement Register */
#define SPR_SDR1 0x019
#define SPR_SRR0 0x01a /* RW: Exception save/restore reg 0 */
#define SPR_SRR1 0x01b /* RW: Exception save/restore reg 1 */