From patchwork Thu Jan 4 11:28:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5Dl0Kllz9sQm for ; Thu, 4 Jan 2018 22:29:43 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5Dk6FJszDqxN for ; Thu, 4 Jan 2018 22:29:42 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5CR6zPZzDqxJ for ; Thu, 4 Jan 2018 22:28:35 +1100 (AEDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSUP4108445 for ; Thu, 4 Jan 2018 06:28:33 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2f9kbxr4vr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:33 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:24 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSOdQ33882280; Thu, 4 Jan 2018 11:28:24 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 605D311C04A; Thu, 4 Jan 2018 11:22:21 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A2DF11C054; Thu, 4 Jan 2018 11:22:20 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:20 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:01 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0016-0000-0000-000005139AC2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0017-0000-0000-0000284FE6E0 Message-Id: <1515065286-8656-5-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 4/9] SLW: Use wakeup_engine state to handle errors in wakeup engine X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Patch introduces wakeup_engine_state which replaces a bool has_wakeup_engine. wakeup_engine_state can have 3 states : - WAKEUP_ENGINE_PRESENT : When everything is good. - WAKEUP_ENGINE_NOT_PRESENT : When wakeup_engine is not correctly detected. - WAKEUP_ENGINE_FAILED : If any operation on wakeup_engine failed. Signed-off-by: Akshay Adiga --- hw/slw.c | 38 ++++++++++++++------------------------ include/skiboot.h | 8 ++++++++ 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index 02aa67ea..119f1e28 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -40,7 +40,7 @@ static uint32_t slw_saved_reset[MAX_RESET_PATCH_SIZE]; static bool slw_current_le = false; -bool has_wakeup_engine = true; +enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; /* SLW timer related stuff */ static bool slw_has_timer; @@ -931,20 +931,8 @@ void add_cpu_idle_state_properties(void) nr_states = ARRAY_SIZE(power7_cpu_idle_states); } - /* - * Enable deep idle states only if : - * P8 : slw image is intact - * P9 : homer_base is set - */ - if (!(proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)) { - if (proc_gen == proc_gen_p9) - has_wakeup_engine = !!(chip->homer_base); - else /* (proc_gen == proc_gen_p8) */ - has_wakeup_engine = (chip->slw_base && chip->slw_bar_size && - chip->slw_image_size); - } else { - has_wakeup_engine = false; - } + if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) + wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; /* * Currently we can't append strings and cells to dt properties. @@ -972,7 +960,7 @@ void add_cpu_idle_state_properties(void) if (has_stop_inst) { /* Power 9 / POWER ISA 3.0 */ supported_states_mask = OPAL_PM_STOP_INST_FAST; - if (has_wakeup_engine) + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) supported_states_mask |= OPAL_PM_STOP_INST_DEEP; } else { /* Power 7 and Power 8 */ @@ -980,7 +968,7 @@ void add_cpu_idle_state_properties(void) if (can_sleep) supported_states_mask |= OPAL_PM_SLEEP_ENABLED | OPAL_PM_SLEEP_ENABLED_ER1; - if (has_wakeup_engine) + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) supported_states_mask |= OPAL_PM_WINKLE_ENABLED; } for (i = 0; i < nr_states; i++) { @@ -1476,10 +1464,10 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) assert(chip); if (proc_gen == proc_gen_p9) { - if (!chip->homer_base) { + if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: HOMER base not set %x\n", - chip->id); + "SLW: wakeup_engine in bad state=%d chip=%x\n", + wakeup_engine_state,chip->id); return OPAL_INTERNAL_ERROR; } rc = p9_stop_save_cpureg((void *)chip->homer_base, @@ -1710,16 +1698,18 @@ void slw_init(void) if (proc_gen == proc_gen_p8) { for_each_chip(chip) { slw_init_chip_p8(chip); - has_wakeup_engine &= slw_image_check_p8(chip); - if (has_wakeup_engine) + if(slw_image_check_p8(chip)) + wakeup_engine_state = WAKEUP_ENGINE_PRESENT; + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) slw_late_init_p8(chip); } slw_init_timer(); } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); - has_wakeup_engine &= slw_image_check_p9(chip); - if (has_wakeup_engine) + if(slw_image_check_p9(chip)) + wakeup_engine_state = WAKEUP_ENGINE_PRESENT; + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) slw_late_init_p9(chip); } } diff --git a/include/skiboot.h b/include/skiboot.h index db913258..90deff78 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -297,6 +297,14 @@ extern void prd_register_reserved_memory(void); /* Flatten device-tree */ extern void *create_dtb(const struct dt_node *root, bool exclusive); +/* Track failure in Wakup engine */ +enum wakeup_engine_states { + WAKEUP_ENGINE_NOT_PRESENT, + WAKEUP_ENGINE_PRESENT, + WAKEUP_ENGINE_FAILED +}; +extern enum wakeup_engine_states wakeup_engine_state; + /* SLW reinit function for switching core settings */ extern int64_t slw_reinit(uint64_t flags);