From patchwork Wed Dec 21 05:35:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 707651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tk3LP2T40z9t0v for ; Wed, 21 Dec 2016 16:36:45 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="u8MSl49x"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3tk3LP1QP5zDwVX for ; Wed, 21 Dec 2016 16:36:45 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="u8MSl49x"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mail-pf0-x241.google.com (mail-pf0-x241.google.com [IPv6:2607:f8b0:400e:c00::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3tk3Km5Rk8zDwVR for ; Wed, 21 Dec 2016 16:36:12 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="u8MSl49x"; dkim-atps=neutral Received: by mail-pf0-x241.google.com with SMTP id y68so10261178pfb.1 for ; Tue, 20 Dec 2016 21:36:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K4vp47JvHwxSePGaazppPW/bBVL+MNxQ47kZQCLPSTI=; b=u8MSl49xSKTaQfmf5GrqR3ACTVl4mT3Er8vHZI3+2DipzPdQyVgBcEJllgAtDWLsEJ jTjKRaP2W0vfMu/VwvkqBnFqV31rR9Hwm0WdTT98/8h7IXqQoB2oq+g2jHUwFOfu5LmD 8ypBc0PpQjKP/5WYHCG1us6j28JlOmrgwLARxTDDbYaNKyFElEAlemfU0Tq4ffVb8IVh iApbXylwY0PRy3yZaVrFpS2uorX7hKkHz0AeCwsWvGgRf0eKPO3zjpNY4ZAPlwTk51Bi KFTOFyvcDRodAlGmBUn0+ub+6cZSvorCTOvLmNW7B5XlMnS9UszsTXL8LivXH6RrpOZO wDUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K4vp47JvHwxSePGaazppPW/bBVL+MNxQ47kZQCLPSTI=; b=cm1ozQsAXyLgVkvndKp6HjnZ+l0IxXULH+hXvPKgLvcqwh4iPlASelxaFU0uFZ3bmq 32keBoTdVnZOW2IDMYEZ0ZCZntn7yJrAbZzEHR2L0JUpp6LlK+6ziY6YPmSQ5axTItoa VwKoHp93UWFe51yBhkYq9i9JJLNsM5ZgsaYJXudlxgVIXnM1oQraa0DlTW52umhaj1x5 5OEi2cSmlK1popBj+pSiNvjf+jnonSTjz6AWkJHbJsZJJx64Zj22vK4PN/EOiR7tImip 5AIUBQsYxlApegMe20W8zAsdJ8IpIdM8Vzq5F7csxp0ivaCiRn5fDA7HifW6KFZG+M+d /Lvw== X-Gm-Message-State: AIkVDXKAbeR0UZcPa9SlaD96c5rhVUT+2Bxj4GxYDA8WKcQnwTn08fRfYhRk2flPzglOEA== X-Received: by 10.99.97.196 with SMTP id v187mr2926692pgb.175.1482298570896; Tue, 20 Dec 2016 21:36:10 -0800 (PST) Received: from flat-canetoad.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id i76sm42962150pfk.89.2016.12.20.21.36.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Dec 2016 21:36:10 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 21 Dec 2016 16:35:37 +1100 Message-Id: <1482298544-8418-4-git-send-email-oohall@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482298544-8418-1-git-send-email-oohall@gmail.com> References: <1482298544-8418-1-git-send-email-oohall@gmail.com> Subject: [Skiboot] [RFC PATCH 03/10] core/test: make cpu.h usable in tests X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Adds an #ifdef around this_cpu() so that it can be used inside test code and fakes out the inline assembly used for barrier instructions and setting the SMT priorities. Signed-off-by: Oliver O'Halloran --- include/cpu.h | 5 +++++ include/processor.h | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/cpu.h b/include/cpu.h index f649a13e6231..eb9551405742 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -189,7 +189,12 @@ extern u8 get_available_nr_cores_in_chip(u32 chip_id); core = next_available_core_in_chip(core, chip_id)) /* Return the caller CPU (only after init_cpu_threads) */ +#ifndef __TEST__ register struct cpu_thread *__this_cpu asm("r13"); +#else +static struct cpu_thread fake_cpu; +static struct cpu_thread *__this_cpu = &fake_cpu; +#endif static inline __nomcount struct cpu_thread *this_cpu(void) { return __this_cpu; diff --git a/include/processor.h b/include/processor.h index 3942268a114a..5d20ffb56dbd 100644 --- a/include/processor.h +++ b/include/processor.h @@ -200,6 +200,8 @@ #else /* __ASSEMBLY__ */ +#ifndef __TEST__ + #include #include @@ -318,6 +320,23 @@ static inline void st_le32(uint32_t *addr, uint32_t val) asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr)); } +#else /* __TEST__ */ + +#define smt_low() +#define smt_medium() +#define smt_high() +#define smt_medium_high() +#define smt_medium_low() +#define smt_extra_high() +#define smt_very_low() + +#define eieio() +#define sync() +#define lwsync() +#define isync() + +#endif /* __TEST__ */ + #endif /* __ASSEMBLY__ */ #endif /* __PROCESSOR_H */