From patchwork Tue Apr 26 01:56:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 614760 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qv5pW4NJyz9t5w for ; Tue, 26 Apr 2016 11:58:11 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3qv5pW3g2JzDqBC for ; Tue, 26 Apr 2016 11:58:11 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) (using TLSv1.2 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3qv5pF3mcTzDq64 for ; Tue, 26 Apr 2016 11:57:57 +1000 (AEST) Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 26 Apr 2016 11:57:56 +1000 Received: from d23dlp02.au.ibm.com (202.81.31.213) by e23smtp07.au.ibm.com (202.81.31.204) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Tue, 26 Apr 2016 11:57:54 +1000 X-IBM-Helo: d23dlp02.au.ibm.com X-IBM-MailFrom: gwshan@linux.vnet.ibm.com X-IBM-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay10.au.ibm.com (d23relay10.au.ibm.com [9.190.26.77]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 8878B2BB0057 for ; Tue, 26 Apr 2016 11:57:53 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u3Q1vitE28508320 for ; Tue, 26 Apr 2016 11:57:53 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u3Q1vK6m027268 for ; Tue, 26 Apr 2016 11:57:20 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u3Q1vKKQ026258; Tue, 26 Apr 2016 11:57:20 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 8F2ECA028C; Tue, 26 Apr 2016 11:56:55 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 8B836E3A27; Tue, 26 Apr 2016 11:56:55 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 79AFF941D0E; Tue, 26 Apr 2016 11:56:55 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Tue, 26 Apr 2016 11:56:52 +1000 Message-Id: <1461635814-4623-2-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1461635814-4623-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1461635814-4623-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16042601-0025-0000-0000-00000463B759 Subject: [Skiboot] [PATCH 2/4] PCI: Move PHB lock to generic layer X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" All kinds of PHBs are maintaining a spinlock. At mean while, the spinlock is acquired or released by backends for phb_ops->lock() or phb_ops->unlock(). There're no difference of the logic on all kinds of PHBs. So it's reasonable to maintain the lock in the generic layer (struct phb). This moves lock from specific PHB to generic one. The spinlock is initialized when the generic PHB is registered in pci_register_phb(). Also, two inline functions phb_{lock, unlock}() are introduced to acquire/release it. No logical changes introduced. Signed-off-by: Gavin Shan --- core/hmi.c | 5 +-- core/pci-opal.c | 113 ++++++++++++++++++++++++------------------------- core/pci.c | 1 + hw/npu-hw-procedures.c | 1 - hw/npu.c | 17 -------- hw/p7ioc-phb.c | 28 ++---------- hw/phb3.c | 20 --------- include/npu.h | 1 - include/p7ioc.h | 2 - include/pci.h | 18 +++++--- include/phb3.h | 1 - 11 files changed, 75 insertions(+), 132 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 1817ab1..99b3a07 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -269,9 +268,9 @@ static int handle_capp_recoverable(int chip_id) if ((mask & (1 << phb_index)) && (chip_id == dt_chip_id)) { phb = pci_get_phb(phb_id); - phb->ops->lock(phb); + phb_lock(phb); phb->ops->set_capp_recovery(phb); - phb->ops->unlock(phb); + phb_unlock(phb); return 1; } } diff --git a/core/pci-opal.c b/core/pci-opal.c index 75c689e..072d150 100644 --- a/core/pci-opal.c +++ b/core/pci-opal.c @@ -19,7 +19,6 @@ #include #include #include -#include #define OPAL_PCICFG_ACCESS(op, cb, type) \ static int64_t opal_pci_config_##op(uint64_t phb_id, \ @@ -31,9 +30,9 @@ static int64_t opal_pci_config_##op(uint64_t phb_id, \ \ if (!phb) \ return OPAL_PARAMETER; \ - phb->ops->lock(phb); \ + phb_lock(phb); \ rc = phb->ops->cfg_##cb(phb, bus_dev_func, offset, data); \ - phb->ops->unlock(phb); \ + phb_unlock(phb); \ pci_put_phb(phb); \ \ return rc; \ @@ -85,10 +84,10 @@ static int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, return OPAL_PARAMETER; if (!phb->ops->eeh_freeze_status) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->eeh_freeze_status(phb, pe_number, freeze_state, pci_error_type, NULL, phb_status); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -105,9 +104,9 @@ static int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, return OPAL_PARAMETER; if (!phb->ops->eeh_freeze_clear) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->eeh_freeze_clear(phb, pe_number, eeh_action_token); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -124,9 +123,9 @@ static int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number, return OPAL_PARAMETER; if (!phb->ops->eeh_freeze_set) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->eeh_freeze_set(phb, pe_number, eeh_action_token); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -149,9 +148,9 @@ static int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) return OPAL_PARAMETER; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->err_inject(phb, pe_no, type, func, addr, mask); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -168,9 +167,9 @@ static int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, return OPAL_PARAMETER; if (!phb->ops->phb_mmio_enable) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->phb_mmio_enable(phb, window_type, window_num, enable); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -191,10 +190,10 @@ static int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, return OPAL_PARAMETER; if (!phb->ops->set_phb_mem_window) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_phb_mem_window(phb, window_type, window_num, addr, pci_addr, size); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -213,10 +212,10 @@ static int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, return OPAL_PARAMETER; if (!phb->ops->map_pe_mmio_window) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->map_pe_mmio_window(phb, pe_number, window_type, window_num, segment_num); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -247,10 +246,10 @@ static int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, return OPAL_PARAMETER; if (!phb->ops->set_pe) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_pe(phb, pe_number, bus_dev_func, bus_compare, dev_compare, func_compare, pe_action); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -267,9 +266,9 @@ static int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, return OPAL_PARAMETER; if (!phb->ops->set_peltv) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_peltv(phb, parent_pe, child_pe, state); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -286,9 +285,9 @@ static int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, return OPAL_PARAMETER; if (!phb->ops->set_mve) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_mve(phb, mve_number, pe_number); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -305,9 +304,9 @@ static int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, return OPAL_PARAMETER; if (!phb->ops->set_mve_enable) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_mve_enable(phb, mve_number, state); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -344,9 +343,9 @@ static int64_t opal_pci_msi_eoi(uint64_t phb_id, return OPAL_PARAMETER; if (!phb->ops->pci_msi_eoi) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->pci_msi_eoi(phb, hwirq); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -363,9 +362,9 @@ static int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, return OPAL_PARAMETER; if (!phb->ops->set_xive_pe) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_xive_pe(phb, pe_number, xive_num); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -382,9 +381,9 @@ static int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, return OPAL_PARAMETER; if (!phb->ops->get_xive_source) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->get_xive_source(phb, xive_num, interrupt_source_number); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -402,10 +401,10 @@ static int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, return OPAL_PARAMETER; if (!phb->ops->get_msi_32) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->get_msi_32(phb, mve_number, xive_num, msi_range, msi_address, message_data); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -423,10 +422,10 @@ static int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, return OPAL_PARAMETER; if (!phb->ops->get_msi_64) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->get_msi_64(phb, mve_number, xive_num, msi_range, msi_address, message_data); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -447,11 +446,11 @@ static int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, return OPAL_PARAMETER; if (!phb->ops->map_pe_dma_window) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->map_pe_dma_window(phb, pe_number, window_id, tce_levels, tce_table_addr, tce_table_size, tce_page_size); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -471,10 +470,10 @@ static int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, return OPAL_PARAMETER; if (!phb->ops->map_pe_dma_window_real) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->map_pe_dma_window_real(phb, pe_number, window_id, pci_start_addr, pci_mem_size); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -495,7 +494,7 @@ static int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, assert_state != OPAL_DEASSERT_RESET) return OPAL_PARAMETER; - phb->ops->lock(phb); + phb_lock(phb); switch(reset_scope) { case OPAL_RESET_PHB_COMPLETE: @@ -554,7 +553,7 @@ static int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, default: rc = OPAL_UNSUPPORTED; } - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return (rc > 0) ? tb_to_msecs(rc) : rc; @@ -573,9 +572,9 @@ static int64_t opal_pci_reinit(uint64_t phb_id, if (!phb->ops || !phb->ops->pci_reinit) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->pci_reinit(phb, reinit_scope, data); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -592,9 +591,9 @@ static int64_t opal_pci_poll(uint64_t phb_id) if (!phb->ops || !phb->ops->poll) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->poll(phb); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); /* Return milliseconds for caller to sleep: round up */ @@ -619,9 +618,9 @@ static int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, return OPAL_PARAMETER; if (!phb->ops->set_phb_tce_memory) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_phb_tce_memory(phb, tce_mem_addr, tce_mem_size); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -639,9 +638,9 @@ static int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, return OPAL_PARAMETER; if (!phb->ops->get_diag_data) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->get_diag_data(phb, diag_buffer, diag_buffer_len); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -659,9 +658,9 @@ static int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, return OPAL_PARAMETER; if (!phb->ops->get_diag_data2) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->get_diag_data2(phb, diag_buffer, diag_buffer_len); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -678,12 +677,12 @@ static int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, return OPAL_PARAMETER; if (!phb->ops->next_error) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); opal_pci_eeh_clear_evt(phb_id); rc = phb->ops->next_error(phb, first_frozen_pe, pci_error_type, severity); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -703,10 +702,10 @@ static int64_t opal_pci_eeh_freeze_status2(uint64_t phb_id, uint64_t pe_number, return OPAL_PARAMETER; if (!phb->ops->eeh_freeze_status) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->eeh_freeze_status(phb, pe_number, freeze_state, pci_error_type, severity, phb_status); - phb->ops->unlock(phb); + phb_unlock(phb); pci_put_phb(phb); return rc; @@ -723,9 +722,9 @@ static int64_t opal_pci_set_phb_capi_mode(uint64_t phb_id, uint64_t mode, uint64 if (!phb->ops->set_capi_mode) return OPAL_UNSUPPORTED; - phb->ops->lock(phb); + phb_lock(phb); rc = phb->ops->set_capi_mode(phb, mode, pe_number); - phb->ops->unlock(phb); + phb_unlock(phb); return rc; } opal_call(OPAL_PCI_SET_PHB_CAPI_MODE, opal_pci_set_phb_capi_mode, 3); diff --git a/core/pci.c b/core/pci.c index e2fe287..66c2470 100644 --- a/core/pci.c +++ b/core/pci.c @@ -824,6 +824,7 @@ int64_t pci_register_phb(struct phb *phb, int opal_id) dt_add_property_cells(phb->dt_node, "ibm,opal-phbid", 0, phb->opal_id); PCIDBG(phb, 0, "PCI: Registered PHB\n"); + init_lock(&phb->lock); list_head_init(&phb->devices); return OPAL_SUCCESS; diff --git a/hw/npu-hw-procedures.c b/hw/npu-hw-procedures.c index ba87d43..4dbb4ba 100644 --- a/hw/npu-hw-procedures.c +++ b/hw/npu-hw-procedures.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/hw/npu.c b/hw/npu.c index a3898b1..14d49a7 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -28,7 +28,6 @@ #include #include #include -#include #include /* @@ -197,20 +196,6 @@ static uint64_t get_bar_size(uint64_t bar) return (1 << GETFIELD(NX_MMIO_BAR_SIZE, bar)) * 0x10000; } -static void npu_lock(struct phb *phb) -{ - struct npu *p = phb_to_npu(phb); - - lock(&p->lock); -} - -static void npu_unlock(struct phb *phb) -{ - struct npu *p = phb_to_npu(phb); - - unlock(&p->lock); -} - /* Update the changes of the device BAR to link BARs */ static void npu_dev_bar_update(uint32_t gcid, struct npu_dev_bar *bar, bool enable) @@ -1102,8 +1087,6 @@ static int64_t npu_err_inject(struct phb *phb, uint32_t pe_num, } static const struct phb_ops npu_ops = { - .lock = npu_lock, - .unlock = npu_unlock, .cfg_read8 = npu_dev_cfg_read8, .cfg_read16 = npu_dev_cfg_read16, .cfg_read32 = npu_dev_cfg_read32, diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c index 97e4885..bad7d0a 100644 --- a/hw/p7ioc-phb.c +++ b/hw/p7ioc-phb.c @@ -54,24 +54,6 @@ static inline uint64_t p7ioc_set_sm_timeout(struct p7ioc_phb *p, uint64_t dur) return dur; } -/* - * Lock callbacks. Allows the OPAL API handlers to lock the - * PHB around calls such as config space, EEH, etc... - */ -static void p7ioc_phb_lock(struct phb *phb) -{ - struct p7ioc_phb *p = phb_to_p7ioc_phb(phb); - - lock(&p->lock); -} - -static void p7ioc_phb_unlock(struct phb *phb) -{ - struct p7ioc_phb *p = phb_to_p7ioc_phb(phb); - - unlock(&p->lock); -} - static bool p7ioc_phb_fenced(struct p7ioc_phb *p) { struct p7ioc *ioc = p->ioc; @@ -2569,8 +2551,6 @@ static int64_t p7ioc_papr_errinjct_reset(struct phb *phb) } static const struct phb_ops p7ioc_phb_ops = { - .lock = p7ioc_phb_lock, - .unlock = p7ioc_phb_unlock, .cfg_read8 = p7ioc_pcicfg_read8, .cfg_read16 = p7ioc_pcicfg_read16, .cfg_read32 = p7ioc_pcicfg_read32, @@ -2750,11 +2730,11 @@ static void p7ioc_phb_err_interrupt(void *data, uint32_t isn) * Check if there's an error pending and update PHB fence * state and return, the ER error is drowned at this point */ - lock(&p->lock); + phb_lock(&p->phb); if (p7ioc_phb_fenced(p)) { p->state = P7IOC_PHB_STATE_FENCED; PHBERR(p, "ER error ignored, PHB fenced\n"); - unlock(&p->lock); + phb_unlock(&p->phb); return; } @@ -2764,7 +2744,7 @@ static void p7ioc_phb_err_interrupt(void *data, uint32_t isn) * overwriting the errors from IOC. */ if (!p7ioc_phb_err_pending(p)) { - unlock(&p->lock); + phb_unlock(&p->phb); return; } @@ -2781,7 +2761,7 @@ static void p7ioc_phb_err_interrupt(void *data, uint32_t isn) p->err.err_bit = 0; p7ioc_phb_set_err_pending(p, true); } - unlock(&p->lock); + phb_unlock(&p->phb); } /* MSIs (OS owned) */ diff --git a/hw/phb3.c b/hw/phb3.c index 598dab7..91fc6bf 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -60,24 +60,6 @@ static void phb3_init_hw(struct phb3 *p, bool first_init); #define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB#%04x: " fmt, \ (p)->phb.opal_id, ## a) -/* - * Lock callbacks. Allows the OPAL API handlers to lock the - * PHB around calls such as config space, EEH, etc... - */ -static void phb3_lock(struct phb *phb) -{ - struct phb3 *p = phb_to_phb3(phb); - - lock(&p->lock); -} - -static void phb3_unlock(struct phb *phb) -{ - struct phb3 *p = phb_to_phb3(phb); - - unlock(&p->lock); -} - /* Helper to select an IODA table entry */ static inline void phb3_ioda_sel(struct phb3 *p, uint32_t table, uint32_t addr, bool autoinc) @@ -3503,8 +3485,6 @@ static int64_t phb3_set_capp_recovery(struct phb *phb) } static const struct phb_ops phb3_ops = { - .lock = phb3_lock, - .unlock = phb3_unlock, .cfg_read8 = phb3_pcicfg_read8, .cfg_read16 = phb3_pcicfg_read16, .cfg_read32 = phb3_pcicfg_read32, diff --git a/include/npu.h b/include/npu.h index 0b2d984..ff6201e 100644 --- a/include/npu.h +++ b/include/npu.h @@ -154,7 +154,6 @@ struct npu_dev { struct npu { uint32_t flags; uint32_t index; - struct lock lock; uint32_t chip_id; uint64_t xscom_base; uint64_t at_xscom; diff --git a/include/p7ioc.h b/include/p7ioc.h index c35ee11..85ea591 100644 --- a/include/p7ioc.h +++ b/include/p7ioc.h @@ -19,7 +19,6 @@ #include #include -#include #include @@ -298,7 +297,6 @@ struct p7ioc_phb { uint32_t rev; /* Both major and minor have 2 bytes */ void *regs_asb; void *regs; /* AIB regs */ - struct lock lock; uint32_t buid_lsi; uint32_t buid_msi; uint64_t io_base; diff --git a/include/pci.h b/include/pci.h index 7b9d088..b9e6ac6 100644 --- a/include/pci.h +++ b/include/pci.h @@ -19,6 +19,7 @@ #include #include +#include #include /* PCI Slot Info: Wired Lane Values @@ -232,12 +233,6 @@ extern int last_phb_id; struct phb_ops { /* - * Locking. This is called around OPAL accesses - */ - void (*lock)(struct phb *phb); - void (*unlock)(struct phb *phb); - - /* * Config space ops */ int64_t (*cfg_read8)(struct phb *phb, uint32_t bdfn, @@ -461,6 +456,7 @@ struct phb { int opal_id; uint32_t scan_map; enum phb_type phb_type; + struct lock lock; struct list_head devices; const struct phb_ops *ops; struct pci_lsi_state lstate; @@ -476,6 +472,16 @@ struct phb { void *platform_data; }; +static inline void phb_lock(struct phb *phb) +{ + lock(&phb->lock); +} + +static inline void phb_unlock(struct phb *phb) +{ + unlock(&phb->lock); +} + /* Config space ops wrappers */ static inline int64_t pci_cfg_read8(struct phb *phb, uint32_t bdfn, uint32_t offset, uint8_t *data) diff --git a/include/phb3.h b/include/phb3.h index 44ac52b..8b08796 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -274,7 +274,6 @@ struct phb3 { uint64_t pe_xscom; /* XSCOM bases */ uint64_t pci_xscom; uint64_t spci_xscom; - struct lock lock; uint64_t mm0_base; /* Full MM window to PHB */ uint64_t mm0_size; /* '' '' '' */ uint64_t mm1_base; /* Full MM window to PHB */