From patchwork Thu Jul 16 23:12:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 496951 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1323E1402B5 for ; Fri, 17 Jul 2015 09:13:42 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id EDE2E1A0EF5 for ; Fri, 17 Jul 2015 09:13:41 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp01.au.ibm.com (e23smtp01.au.ibm.com [202.81.31.143]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id E06B71A0784 for ; Fri, 17 Jul 2015 09:13:34 +1000 (AEST) Received: from /spool/local by e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 17 Jul 2015 09:13:31 +1000 X-Helo: d23dlp03.au.ibm.com X-MailFrom: gwshan@linux.vnet.ibm.com X-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 670B1357804C for ; Fri, 17 Jul 2015 09:13:31 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t6GNDNJK57671852 for ; Fri, 17 Jul 2015 09:13:32 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t6GNCw4S030858 for ; Fri, 17 Jul 2015 09:12:58 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t6GNCwTM030410; Fri, 17 Jul 2015 09:12:58 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 1D836A019B; Fri, 17 Jul 2015 09:12:34 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 04218E38E6; Fri, 17 Jul 2015 09:12:34 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id DB6689412EC; Fri, 17 Jul 2015 09:12:33 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 17 Jul 2015 09:12:31 +1000 Message-Id: <1437088352-6150-1-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15071623-1618-0000-0000-0000026E44BB Subject: [Skiboot] [PATCH 1/2] hw/phb3: Change reserved PE to 255 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently, we have reserved PE#0 to which all RIDs are mapped prior to PE assignment request from kernel. The last M64 BAR is configured to have shared mode. So we have to cut off the first M64 segment, which corresponds to reserved PE#0 in kernel. If the first BAR (for example PF's IOV BAR) requires huge alignment in kernel, we have to waste huge M64 space to accomodate the alignment. If we have reserved PE#256, the waste of M64 space will be avoided. Signed-off-by: Gavin Shan --- hw/phb3.c | 21 ++++++++++++++++----- include/phb3.h | 1 + 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index cdc20e8..6bf73bf 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -559,7 +559,8 @@ static void phb3_init_ioda_cache(struct phb3 *p) * ever let a live FF RTT even temporarily when resetting * for EEH etc... (HW278969). */ - memset(p->rte_cache, 0x00, RTT_TABLE_SIZE); + for (i = 0; i < ARRAY_SIZE(p->rte_cache); i++) + p->rte_cache[i] = PHB3_RESERVED_PE_NUM; memset(p->peltv_cache, 0x0, sizeof(p->peltv_cache)); /* Disable all LSI */ @@ -1792,7 +1793,8 @@ static int64_t phb3_set_pe(struct phb *phb, for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++) p->rte_cache[idx] = pe_num; } else { - memset(p->rte_cache, 0, RTT_TABLE_SIZE); + for ( idx = 0; idx < ARRAY_SIZE(p->rte_cache); idx++) + p->rte_cache[idx] = PHB3_RESERVED_PE_NUM; } memcpy((void *)p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE); } else { @@ -1800,7 +1802,10 @@ static int64_t phb3_set_pe(struct phb *phb, for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++, rte++) { if ((idx & mask) != val) continue; - p->rte_cache[idx] = (action ? pe_num : 0); + if (action == OPAL_MAP_PE) + p->rte_cache[idx] = pe_num; + else + p->rte_cache[idx] = PHB3_RESERVED_PE_NUM; *rte = p->rte_cache[idx]; } } @@ -4026,6 +4031,9 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) static void phb3_allocate_tables(struct phb3 *p) { + uint16_t *rte; + uint32_t i; + /* XXX Our current memalign implementation sucks, * * It will do the job, however it doesn't support freeing @@ -4034,7 +4042,9 @@ static void phb3_allocate_tables(struct phb3 *p) */ p->tbl_rtt = (uint64_t)local_alloc(p->chip_id, RTT_TABLE_SIZE, RTT_TABLE_SIZE); assert(p->tbl_rtt); - memset((void *)p->tbl_rtt, 0, RTT_TABLE_SIZE); + rte = (uint16_t *)(p->tbl_rtt); + for (i = 0; i < RTT_TABLE_ENTRIES; i++, rte++) + *rte = PHB3_RESERVED_PE_NUM; p->tbl_peltv = (uint64_t)local_alloc(p->chip_id, PELTV_TABLE_SIZE, PELTV_TABLE_SIZE); assert(p->tbl_peltv); @@ -4100,7 +4110,8 @@ static void phb3_add_properties(struct phb3 *p) dt_add_property(np, "ibm,opal-single-pe", NULL, 0); //dt_add_property_cells(np, "ibm,opal-msi-ports", 2048); dt_add_property_cells(np, "ibm,opal-num-pes", 256); - dt_add_property_cells(np, "ibm,opal-reserved-pe", 0); + dt_add_property_cells(np, "ibm,opal-reserved-pe", + PHB3_RESERVED_PE_NUM); dt_add_property_cells(np, "ibm,opal-msi-ranges", p->base_msi, PHB3_MSI_IRQ_COUNT); tkill = reg + PHB_TCE_KILL; diff --git a/include/phb3.h b/include/phb3.h index ea3ad87..c15f5d2 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -148,6 +148,7 @@ struct rtt_entry { * capability register later. */ #define PHB3_MAX_PE_NUM 256 +#define PHB3_RESERVED_PE_NUM 255 /* * State structure for a PHB