From patchwork Sun Jul 5 16:55:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: maddy X-Patchwork-Id: 491329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46262140D5F for ; Mon, 6 Jul 2015 02:56:51 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 1DAED1A0D75 for ; Mon, 6 Jul 2015 02:56:51 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 865371A0751 for ; Mon, 6 Jul 2015 02:56:42 +1000 (AEST) Received: from /spool/local by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 6 Jul 2015 02:56:38 +1000 X-Helo: d23dlp03.au.ibm.com X-MailFrom: maddy@linux.vnet.ibm.com X-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 0808F3578048 for ; Mon, 6 Jul 2015 02:56:37 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t65GuUAJ3408140 for ; Mon, 6 Jul 2015 02:56:38 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t65Gu4Pj030148 for ; Mon, 6 Jul 2015 02:56:04 +1000 Received: from SrihariMadhavan.ibm.com ([9.77.67.184]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t65Gtw4p029878; Mon, 6 Jul 2015 02:56:02 +1000 From: Madhavan Srinivasan To: stewart@linux.vnet.ibm.com, jk@ozlabs.org Date: Sun, 5 Jul 2015 22:25:23 +0530 Message-Id: <1436115333-18657-2-git-send-email-maddy@linux.vnet.ibm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1436115333-18657-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1436115333-18657-1-git-send-email-maddy@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15070516-0017-0000-0000-00000177E5B3 Subject: [Skiboot] [RESEND PATCH 01/11]ibm-fsp/firenze: nest data structure definitions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Patch adds the data structures and macros needed for Nest instrumentation support. Patch creates new file in include dir called "nest.h". Signed-off-by: Madhavan Srinivasan --- include/nest.h | 219 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 include/nest.h diff --git a/include/nest.h b/include/nest.h new file mode 100644 index 0000000..0dcd946 --- /dev/null +++ b/include/nest.h @@ -0,0 +1,219 @@ +/* Copyright 2015 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __NEST_H +#define __NEST_H + +/* + * Power8 has Nest Instrumentation support with which per-chip + * utilisation metrics like memory bandwidth, Xlink/Alink bandwidth and + * many other component metrics can be obtained. These Nest + * counters can be programmed via scoms or HW PORE Engine, + * called PORE_SLW_IMA. + * + * PORE_SLW_IMA: + * PORE_SLW_IMA is a firmware that runs on PORE Engine. + * This firmware programs the nest counter and moves counter values to + * per chip HOMER region in a fixed offset for each unit. Engine + * has a control block structure for communication with Hyperviosr. + */ + +/* + * Control Block structure offset in HOMER IMA Region + */ +#define CB_STRUCT_OFFSET 0x39FC00 +#define CB_STRUCT_CMD 0x39FC08 +#define CB_STRUCT_SPEED 0x39FC10 +#define SLW_IMA_PAUSE 0x2 +#define SLW_IMA_RESUME 0x1 +#define SLW_IMA_NOP 0 +/* + * Control Block Structure: + * + * Name Producer Consumer Values Desc + * IMARunStatus IMA Code Hypervisor 0 Initializing + * 1 Running + * 2 Paused + * + * IMACommand Hypervisor IMA Code 0 NOP + * 1 Resume + * 2 Pause + * 3 Clear and Restart + * + * IMACollection Hypervisor IMA Code 0 128us + * Speed 1 256us + * 2 1ms + * 3 4ms + * 4 16ms + * 5 64ms + * 6 256ms + * 7 1000ms + */ +struct ima_chip_cb +{ + uint64_t ima_chip_run_status; + uint64_t ima_chip_command; + uint64_t ima_chip_collection_speed; +}; + +/* + * PORE_SLW_IMA reserved memory (in HOMER region) + */ +#define SLW_IMA_OFFSET 0x00320000 +#define SLW_IMA_TOTAL_SIZE 0x80000 + +/* + * Counter Storage size (exposed as part of DT) + */ +#define SLW_IMA_SIZE 0x10000 + +/* + * PTS Scoms and values + */ +#define IMA_PTS_SCOM 0x00068009 +#define IMA_PTS_ENABLE 0x00F0000000000000 +#define IMA_PTS_DISABLE 0x00E0000000000000 +#define IMA_PTS_START 0x1 +#define IMA_PTS_STOP 0 +#define IMA_PTS_ERROR -1 + +/* + * Catalogue structures. + * Catalogue is a meta data file provided as part of FW lid. + * This file contains information about the various events the + * HW supports under the "24x7" umbrella. Events are classified under + * 3 different Domains. + * Domain 1 -- Chip Events (PORE_SLW_IMA) + * Domain 2 -- Core Events (24x7 Core IMA) + * Domain 3 -- per-Thread PMU Events + */ + +struct ima_catalog_page_0 { +#define CATALOG_MAGIC 0x32347837 /* "24x7" in ASCII */ + __be32 magic; + __be32 length; /* In 4096 byte pages */ + __be64 version; /* XXX: arbitrary? what's the meaning/useage/purpose? */ + __u8 build_time_stamp[16]; /* "YYYYMMDDHHMMSS\0\0" */ + __u8 reserved2[32]; + __be16 schema_data_offs; /* in 4096 byte pages */ + __be16 schema_data_len; /* in 4096 byte pages */ + __be16 schema_entry_count; + __u8 reserved3[2]; + __be16 event_data_offs; + __be16 event_data_len; + __be16 event_entry_count; + __u8 reserved4[2]; + __be16 group_data_offs; /* in 4096 byte pages */ + __be16 group_data_len; /* in 4096 byte pages */ + __be16 group_entry_count; + __u8 reserved5[2]; + __be16 formula_data_offs; /* in 4096 byte pages */ + __be16 formula_data_len; /* in 4096 byte pages */ + __be16 formula_entry_count; + __u8 reserved6[2]; + __be32 core_event_offset; + __be32 thread_event_offset; + __be32 chip_event_offset; + __be32 core_group_offset; + __be32 thread_group_offset; + __be32 chip_group_offset; +} __packed; + +struct ima_catalogue_group_data { + __be16 length; /* in bytes, must be a multiple of 16 */ + __u8 reserved1[2]; + /* verified_state, unverified_state, caveat_state, broken_state, ... */ + __be32 flags; + __u8 domain; /* Chip = 1, Core = 2 */ + __u8 reserved2[1]; + __be16 event_group_record_start_offs; /* in bytes, must be 8 byte aligned */ + __be16 event_group_record_len; /* in bytes */ + /* in bytes, offset from event_group_record */ + __u8 group_schema_index; + __u8 event_count; + __be16 event_index[16]; /* in bytes */ + __be16 group_name_len; + __u8 remainder[]; + /* __u8 event_name[event_name_len - 2]; */ + /* __be16 event_description_len; */ + /* __u8 event_desc[event_description_len - 2]; */ + /* __be16 detailed_desc_len; */ + /* __u8 detailed_desc[detailed_desc_len - 2]; */ +} __packed; + +struct ima_catalogue_event_data { + __be16 length; /* in bytes, must be a multiple of 16 */ + __be16 formula_index; + __u8 domain; /* Chip = 1, Core = 2 */ + __u8 reserved2[1]; + __be16 event_group_record_offs; /* in bytes, must be 8 byte aligned */ + __be16 event_group_record_len; /* in bytes */ + + /* in bytes, offset from event_group_record */ + __be16 event_counter_offs; + + /* verified_state, unverified_state, caveat_state, broken_state, ... */ + __be32 flags; + + __be16 primary_group_ix; + __be16 group_count; + __be16 event_name_len; + __u8 remainder[]; + /* __u8 event_name[event_name_len - 2]; */ + /* __be16 event_description_len; */ + /* __u8 event_desc[event_description_len - 2]; */ + /* __be16 detailed_desc_len; */ + /* __u8 detailed_desc[detailed_desc_len - 2]; */ +} __packed; + + +#define CHIP_EVENTS_SUPPORTED 1 +#define CHIP_EVENTS_NOT_SUPPORTED 0 + +/* + * Just for optimisation, save only relavent addrs + */ +struct page0_offsets { + char *page0; + char *group_entry; + char *event_entry; + char *thread_event_entry; + char *core_event_entry; + char *chip_event_entry; + char *thread_group_entry; + char *core_group_entry; + char *chip_group_entry; +}; + +#define PAGE0(x) x->page0 +#define GROUP_ENTRY(x) x->group_entry +#define EVENT_ENTRY(x) x->event_entry +#define THREAD_EVENT_ENTRY(x) x->thread_event_entry +#define CORE_EVENT_ENTRY(x) x->core_event_entry +#define CHIP_EVENT_ENTRY(x) x->chip_event_entry +#define THREAD_GROUP_ENTRY(x) x->thread_group_entry +#define CORE_GROUP_ENTRY(x) x->core_group_entry +#define CHIP_GROUP_ENTRY(x) x->chip_group_entry + +/* Event Domains, Chip=1, Core=2 */ +#define DOMAIN_CHIP 1 +#define DOMAIN_CORE 2 + +/* dimm information for utilssation metrics */ +#define MURANO_CENTAUR_DIMM 24000 +#define VENICE_CENTAUR_DIMM 27000 + +#endif /* __NEST_H__ */