From patchwork Thu Jun 4 06:18:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 480437 X-Patchwork-Delegate: benh@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0783A140187 for ; Thu, 4 Jun 2015 16:21:30 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id E267F1A08B2 for ; Thu, 4 Jun 2015 16:21:29 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id A096C1A027C for ; Thu, 4 Jun 2015 16:21:24 +1000 (AEST) Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jun 2015 16:21:23 +1000 Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id AA1B42BB0052 for ; Thu, 4 Jun 2015 16:21:22 +1000 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t546Jxjr51314724 for ; Thu, 4 Jun 2015 16:20:07 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t546JZwc010907 for ; Thu, 4 Jun 2015 16:19:35 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t546JZoM010294; Thu, 4 Jun 2015 16:19:35 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id D8FF2A0271; Thu, 4 Jun 2015 16:19:10 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id E3C4FE387C; Thu, 4 Jun 2015 16:19:10 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id D5B449422B2; Thu, 4 Jun 2015 16:19:10 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Thu, 4 Jun 2015 16:18:53 +1000 Message-Id: <1433398749-15096-2-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1433398749-15096-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1433398749-15096-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15060406-0009-0000-0000-00000183D252 Subject: [Skiboot] [PATCH v7 01/17] platforms/firenze: Fix I2C clock source frequency X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The I2C master clock source frequency is hardcoded to wrong value. The correct frequency should be the nest clock frequency divided by 16 as Ben said. The patch fixes I2C master resource frequency with the help of additional properties "nest-frequency" and "bus-frequency" to root and xscom device node separately. Suggested-by: Benjamin Herrenschmidt Signed-off-by: Gavin Shan --- hdata/spira.c | 19 +++++++++++++++++++ hdata/spira.h | 8 ++++++-- platforms/ibm-fsp/firenze.c | 11 ++++++++++- 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/hdata/spira.c b/hdata/spira.c index b35ca9c..4776de8 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -182,6 +182,7 @@ static struct dt_node *add_xscom_node(uint64_t base, uint32_t hw_id, { struct dt_node *node; uint64_t addr, size; + uint64_t freq; addr = base | ((uint64_t)hw_id << PPC_BITLSHIFT(28)); size = (u64)1 << PPC_BITLSHIFT(28); @@ -213,6 +214,13 @@ static struct dt_node *add_xscom_node(uint64_t base, uint32_t hw_id, } dt_add_property_u64s(node, "reg", addr, size); + /* Derive bus frquency */ + freq = dt_prop_get_u64_def(dt_root, "nest-frequency", 0); + freq /= 4; + if (freq) + dt_add_property_cells(node, "bus-frequency", + hi32(freq), lo32(freq)); + return node; } @@ -693,6 +701,8 @@ static void add_iplparams_sys_params(const void *iplp, struct dt_node *node) const struct iplparams_sysparams *p; u32 sys_type; const char *sys_family; + const struct HDIF_common_hdr *hdif = iplp; + u16 version = be16_to_cpu(hdif->version); p = HDIF_get_idata(iplp, IPLPARAMS_SYSPARAMS, NULL); if (!CHECK_SPPTR(p)) { @@ -732,6 +742,15 @@ static void add_iplparams_sys_params(const void *iplp, struct dt_node *node) } dt_add_property_strings(dt_root, "compatible", "ibm,powernv", sys_family); + + /* Grab nest frequency when available */ + if (version >= 0x005b) { + u64 freq = be32_to_cpu(p->nest_freq_mhz); + + freq *= 1000000; + dt_add_property_cells(dt_root, "nest-frquency", + hi32(freq), lo32(freq)); + } } static void add_iplparams_ipl_params(const void *iplp, struct dt_node *node) diff --git a/hdata/spira.h b/hdata/spira.h index 0916fe3..22433f4 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -239,9 +239,13 @@ struct iplparams_sysparams { __be32 sys_attributes; __be32 mem_scrubbing; __be16 cur_spl_value; - uint8_t pump_mode; + uint8_t pump_mode; /* Reserved */ uint8_t use_pore_sleep; - __be32 pore_image_size; + __be32 pore_image_size; /* Reserved */ + uint8_t vtpm_enabled; + uint8_t hw_page_table_size; /* >= 0x59 */ + __be16 hv_disp_wheel; /* >= 0x58 */ + __be32 nest_freq_mhz; /* >= 0x5b */ } __packed; /* Idata index 1: IPL parameters */ diff --git a/platforms/ibm-fsp/firenze.c b/platforms/ibm-fsp/firenze.c index 8e750ce..1b087fb 100644 --- a/platforms/ibm-fsp/firenze.c +++ b/platforms/ibm-fsp/firenze.c @@ -52,6 +52,7 @@ static unsigned int fsp_pcie_inv_alloc_count; static struct dt_node *dt_create_i2c_master(struct dt_node *n, uint32_t eng_id) { struct dt_node *i2cm; + uint64_t freq; /* Each master registers set is of length 0x20 */ i2cm = dt_new_addr(n, "i2cm", 0xa0000 + eng_id * 0x20); @@ -62,11 +63,19 @@ static struct dt_node *dt_create_i2c_master(struct dt_node *n, uint32_t eng_id) "ibm,power8-i2cm"); dt_add_property_cells(i2cm, "reg", 0xa0000 + eng_id * 0x20, 0x20); - dt_add_property_cells(i2cm, "clock-frequency", 50000000); dt_add_property_cells(i2cm, "chip-engine#", eng_id); dt_add_property_cells(i2cm, "#address-cells", 1); dt_add_property_cells(i2cm, "#size-cells", 0); + /* Derive the clock source frequency */ + freq = dt_prop_get_u64_def(n, "bus-frequency", 0); + freq /= 4; + if (freq) + dt_add_property_cells(i2cm, "clock-frequency", + hi32(freq), lo32(freq)); + else + dt_add_property_cells(i2cm, "clock-frequency", + 125000000); return i2cm; }