From patchwork Wed Apr 29 06:46:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 465909 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A0BFD140320 for ; Wed, 29 Apr 2015 16:47:04 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 8537E1A0DE2 for ; Wed, 29 Apr 2015 16:47:04 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e06smtp13.uk.ibm.com (e06smtp13.uk.ibm.com [195.75.94.109]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 2AE791A0DCC for ; Wed, 29 Apr 2015 16:47:00 +1000 (AEST) Received: from /spool/local by e06smtp13.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 29 Apr 2015 07:46:55 +0100 Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by d06dlp02.portsmouth.uk.ibm.com (Postfix) with ESMTP id 38A04219005C for ; Wed, 29 Apr 2015 07:46:37 +0100 (BST) Received: from d06av05.portsmouth.uk.ibm.com (d06av05.portsmouth.uk.ibm.com [9.149.37.229]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t3T6ksOM1507600 for ; Wed, 29 Apr 2015 06:46:54 GMT Received: from d06av05.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av05.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t3T6ksfc028724 for ; Wed, 29 Apr 2015 00:46:54 -0600 Received: from hermes.kaod.org (sig-9-79-38-167.de.ibm.com [9.79.38.167]) by d06av05.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t3T6krXY028701; Wed, 29 Apr 2015 00:46:53 -0600 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: skiboot@lists.ozlabs.org Date: Wed, 29 Apr 2015 08:46:56 +0200 Message-Id: <1430290016-27752-1-git-send-email-clg@fr.ibm.com> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15042906-0013-0000-0000-000003D042FB Subject: [Skiboot] [PATCH] dts: add support for p7 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch exposes the DTS of the P7 cores. For this, it simply uses the dts/sensor framework included in OPAL for P8. Signed-off-by: Cédric Le Goater --- This is a good way to exercise the Linux driver on a platform having a different number of threads per core. hw/dts.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) Index: skiboot.git/hw/dts.c =================================================================== --- skiboot.git.orig/hw/dts.c +++ skiboot.git/hw/dts.c @@ -44,6 +44,67 @@ struct dts { int16_t temp; }; +/* Different sensor locations */ +#define P7_CT_ZONE_LSU 0 +#define P7_CT_ZONE_ISU 1 +#define P7_CT_ZONE_IFU 2 +#define P7_CT_ZONE_VFU 3 +#define P7_CT_ZONE_L3C 4 +#define P7_CT_ZONES 5 + +/* Per core Digital Thermal Sensors */ +#define EX_THERM_P7_DTS_RESULT0 0x8050000 +#define EX_THERM_P7_DTS_RESULT1 0x8050001 + +/* + * DTS2 Thermal Sensor Results + * + * 0..7 sensor with id 0. + * 8..15 sensor with id 1. (Only chiplets) + * 16..23 sensor with id 2. (Only chiplets) + * 24..31 sensor with id 3. (Only chiplets) + * 32..39 sensor with id 4. (Only chiplets) + * 40..56 reserved0 + * 57 Trip warning history + * 58 Trip critical history + * 59 Trip fatal history + * 60 reserved1 + * 61..63 ID of worst case DTS2 (Only valid in EX core chiplets) + */ +static int dts_read_core_temp_p7(uint32_t pir, struct dts *dts) +{ + int32_t chip_id = pir_to_chip_id(pir); + int32_t core = pir_to_core_id(pir); + uint64_t dts0; + struct dts temps[P7_CT_ZONES]; + int i; + int rc; + + rc = xscom_read(chip_id, + XSCOM_ADDR_P8_EX(core, EX_THERM_P7_DTS_RESULT0), + &dts0); + if (rc) + return rc; + + temps[P7_CT_ZONE_LSU].temp = (dts0 >> 56) & 0xff; + temps[P7_CT_ZONE_ISU].temp = (dts0 >> 48) & 0xff; + temps[P7_CT_ZONE_IFU].temp = (dts0 >> 40) & 0xff; + temps[P7_CT_ZONE_VFU].temp = (dts0 >> 32) & 0xff; + temps[P7_CT_ZONE_L3C].temp = (dts0 >> 24) & 0xff; + + /* keep the max DTS */ + for (i = 0; i < P7_CT_ZONES; i++) { + int16_t t = temps[i].temp; + if (t > dts->temp) + dts->temp = t; + } + dts->trip = (dts0 >> 3) & 0xf; + + prlog(PR_TRACE, "DTS: Chip %x Core %x temp:%dC trip:%x\n", + chip_id, core, dts->temp, dts->trip); + + return 0; +} /* Therm mac result masking for DTS (result(0:15) * 0:3 - 0x0 @@ -82,7 +143,7 @@ static void dts_decode_one_dts(uint16_t * Returns the temperature as the max of all 4 zones and a global trip * attribute. */ -static int dts_read_core_temp(uint32_t pir, struct dts *dts) +static int dts_read_core_temp_p8(uint32_t pir, struct dts *dts) { int32_t chip_id = pir_to_chip_id(pir); int32_t core = pir_to_core_id(pir); @@ -131,6 +192,23 @@ static int dts_read_core_temp(uint32_t p return 0; } +static int dts_read_core_temp(uint32_t pir, struct dts *dts) +{ + int rc; + + switch (proc_gen) { + case proc_gen_p7: + rc = dts_read_core_temp_p7(pir, dts); + break; + case proc_gen_p8: + rc = dts_read_core_temp_p8(pir, dts); + break; + default: + assert(false); + } + return rc; +} + /* Different sensor locations */ #define P8_MEM_DTS0 0