diff mbox

Add Naples chip support

Message ID 1428531030.18187.33.camel@kernel.crashing.org
State Accepted
Headers show

Commit Message

Benjamin Herrenschmidt April 8, 2015, 10:10 p.m. UTC 
This adds the PVR and CFAM ID for the Naples chip. Otherwise treated as
a Venice.

This doesn't add the definitions for the new PHB revision yet

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
diff mbox

Patch

diff --git a/asm/head.S b/asm/head.S
index 0b90d22..955c3b5 100644
--- a/asm/head.S
+++ b/asm/head.S
@@ -257,6 +257,8 @@  boot_entry:
 	beq	2f
 	cmpwi	cr0,%r3,PVR_TYPE_P8E
 	beq	2f
+	cmpwi	cr0,%r3,PVR_TYPE_P8NVL
+	beq	2f
 	attn		/* Unsupported CPU type... what do we do ? */
 
 	/* P8 -> 8 threads */
@@ -656,6 +658,8 @@  init_shared_sprs:
 	beq	3f
 	cmpwi	cr0,%r3,PVR_TYPE_P8
 	beq	3f
+	cmpwi	cr0,%r3,PVR_TYPE_P8NVL
+	beq	3f
 	/* Unsupported CPU type... what do we do ? */
 	b	9f
 
diff --git a/core/cpu.c b/core/cpu.c
index 8f684d2..756386b 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -45,6 +45,7 @@  unsigned int cpu_thread_count;
 unsigned int cpu_max_pir;
 struct cpu_thread *boot_cpu;
 static struct lock reinit_lock = LOCK_UNLOCKED;
+static bool hile_supported;
 
 unsigned long cpu_secondary_start __force_data = 0;
 
@@ -359,21 +360,36 @@  void init_boot_cpu(void)
 	pir = mfspr(SPR_PIR);
 	pvr = mfspr(SPR_PVR);
 
-	/* Get a CPU thread count and an initial max PIR based on PVR */
+	/* Get CPU family and other flags based on PVR */
 	switch(PVR_TYPE(pvr)) {
 	case PVR_TYPE_P7:
 	case PVR_TYPE_P7P:
+		proc_gen = proc_gen_p7;
+		break;
+	case PVR_TYPE_P8E:
+	case PVR_TYPE_P8:
+		proc_gen = proc_gen_p8;
+		hile_supported = PVR_VERS_MAJ(mfspr(SPR_PVR)) >= 2;
+		break;
+	case PVR_TYPE_P8NVL:
+		proc_gen = proc_gen_p8;
+		hile_supported = true;
+		break;
+	default:
+		proc_gen = proc_gen_unknown;
+	}
+
+	/* Get a CPU thread count and an initial max PIR based on family */
+	switch(proc_gen) {
+	case proc_gen_p7:
 		cpu_thread_count = 4;
 		cpu_max_pir = SPR_PIR_P7_MASK;
-		proc_gen = proc_gen_p7;
 		prlog(PR_INFO, "CPU: P7 generation processor"
 		      "(max %d threads/core)\n", cpu_thread_count);
 		break;
-	case PVR_TYPE_P8E:
-	case PVR_TYPE_P8:
+	case proc_gen_p8:
 		cpu_thread_count = 8;
 		cpu_max_pir = SPR_PIR_P8_MASK;
-		proc_gen = proc_gen_p8;
 		prlog(PR_INFO, "CPU: P8 generation processor"
 		      "(max %d threads/core)\n", cpu_thread_count);
 		break;
@@ -381,7 +397,6 @@  void init_boot_cpu(void)
 		prerror("CPU: Unknown PVR, assuming 1 thread\n");
 		cpu_thread_count = 1;
 		cpu_max_pir = mfspr(SPR_PIR);
-		proc_gen = proc_gen_unknown;
 	}
 
 	prlog(PR_DEBUG, "CPU: Boot CPU PIR is 0x%04x PVR is 0x%08x\n",
@@ -679,7 +694,7 @@  static int64_t opal_reinit_cpus(uint64_t flags)
 	 * use the HID bit. We use the PVR (we could use the EC level in
 	 * the chip but the PVR is more readily available).
 	 */
-	if (proc_gen == proc_gen_p8 && PVR_VERS_MAJ(mfspr(SPR_PVR)) >= 2 &&
+	if (hile_supported &&
 	    (flags & (OPAL_REINIT_CPUS_HILE_BE | OPAL_REINIT_CPUS_HILE_LE))) {
 		bool hile = !!(flags & OPAL_REINIT_CPUS_HILE_LE);
 
diff --git a/hdata/cpu-common.c b/hdata/cpu-common.c
index e1aa607..e0f335b 100644
--- a/hdata/cpu-common.c
+++ b/hdata/cpu-common.c
@@ -53,6 +53,7 @@  struct dt_node * add_core_common(struct dt_node *cpus,
 		break;
 	case PVR_TYPE_P8E:
 	case PVR_TYPE_P8:
+	case PVR_TYPE_P8NVL:
 		name = "PowerPC,POWER8";
 		break;
 	default:
diff --git a/hdata/test/hdata_to_dt.c b/hdata/test/hdata_to_dt.c
index 4215740..4ca2a10 100644
--- a/hdata/test/hdata_to_dt.c
+++ b/hdata/test/hdata_to_dt.c
@@ -48,6 +48,7 @@  static void *ntuple_addr(const struct spira_ntuple *n);
 #define PVR_TYPE_P7P	0x004a
 #define PVR_TYPE_P8E	0x004b
 #define PVR_TYPE_P8	0x004d
+#define PVR_TYPE_P8NVL	0x004c
 
 #define SPR_PVR		0x11f	/* RO: Processor version register */
 
diff --git a/hw/xscom.c b/hw/xscom.c
index d8af989..6bd71a3 100644
--- a/hw/xscom.c
+++ b/hw/xscom.c
@@ -480,6 +480,10 @@  static void xscom_init_chip_info(struct proc_chip *chip)
 		chip->type = PROC_CHIP_P8_VENICE;
 		assert(proc_gen == proc_gen_p8);
 		break;
+	case 0xd3:
+		chip->type = PROC_CHIP_P8_NAPLES;
+		assert(proc_gen == proc_gen_p8);
+		break;
 	default:
 		printf("CHIP: Unknown chip type 0x%02x !!!\n",
 		       (unsigned char)(val & 0xff));
diff --git a/include/chip.h b/include/chip.h
index 34bd6d9..0547902 100644
--- a/include/chip.h
+++ b/include/chip.h
@@ -87,6 +87,7 @@  enum proc_chip_type {
 	PROC_CHIP_P7P,
 	PROC_CHIP_P8_MURANO,
 	PROC_CHIP_P8_VENICE,
+	PROC_CHIP_P8_NAPLES,
 };
 
 /* Simulator quirks */
diff --git a/include/processor.h b/include/processor.h
index cdc5919..c9e9d0e 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -179,6 +179,7 @@ 
 #define PVR_TYPE_P7P	0x004a
 #define PVR_TYPE_P8E	0x004b /* Murano */
 #define PVR_TYPE_P8	0x004d /* Venice */
+#define PVR_TYPE_P8NVL	0x004c /* Naples */
 
 #ifdef __ASSEMBLY__