From patchwork Fri Feb 27 10:18:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Kerr X-Patchwork-Id: 444237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 04DBB140111 for ; Fri, 27 Feb 2015 21:18:32 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id E28461A00FD for ; Fri, 27 Feb 2015 21:18:31 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from ozlabs.org (ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id E8F281A0071 for ; Fri, 27 Feb 2015 21:18:24 +1100 (AEDT) Received: by ozlabs.org (Postfix, from userid 1023) id BA4A7140111; Fri, 27 Feb 2015 21:18:24 +1100 (AEDT) MIME-Version: 1.0 Message-Id: <1425032299.925449.465688148297.2.gpush@pablo> In-Reply-To: <1425032299.925270.779407368864.1.gpush@pablo> To: skiboot@lists.ozlabs.org From: Jeremy Kerr Date: Fri, 27 Feb 2015 18:18:19 +0800 Cc: Joel Stanley Subject: [Skiboot] [PATCH 2/2] occ: Inform OCC of BMC PNOR ownership requests X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We need to pass the PNOR access status to the OCCs, as they may write to the PNOR in the event of a checkstop. Signed-off-by: Jeremy Kerr --- hw/ipmi/ipmi-sel.c | 3 +++ hw/occ.c | 28 ++++++++++++++++++++++++++++ include/skiboot.h | 7 +++++++ 3 files changed, 38 insertions(+) diff --git a/hw/ipmi/ipmi-sel.c b/hw/ipmi/ipmi-sel.c index c86c2c9..8851dc3 100644 --- a/hw/ipmi/ipmi-sel.c +++ b/hw/ipmi/ipmi-sel.c @@ -195,6 +195,8 @@ static void sel_pnor(uint8_t access) case REQUEST_PNOR: prlog(PR_NOTICE, "IPMI: PNOR access requested\n"); granted = flash_reserve(); + if (granted) + occ_pnor_set_owner(PNOR_OWNER_EXTERNAL); /* Ack the request */ msg = ipmi_mkmsg_simple(IPMI_PNOR_ACCESS_STATUS, &granted, 1); @@ -203,6 +205,7 @@ static void sel_pnor(uint8_t access) case RELEASE_PNOR: prlog(PR_NOTICE, "IPMI: PNOR access released\n"); flash_release(); + occ_pnor_set_owner(PNOR_OWNER_HOST); break; default: prlog(PR_ERR, "IPMI: invalid PNOR access requested: %02x\n", diff --git a/hw/occ.c b/hw/occ.c index 8eb6469..657f2ad 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -537,6 +537,34 @@ static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id) } } +#define PV_OCC_GP0 0x01000000 +#define PV_OCC_GP0_AND 0x01000004 +#define PV_OCC_GP0_OR 0x01000005 +#define PV_OCC_GP0_PNOR_OWNER PPC_BIT(18) /* 1 = OCC / Host, 0 = BMC */ + +static void occ_pnor_set_one_owner(uint32_t chip_id, enum pnor_owner owner) +{ + uint64_t reg, mask; + + if (owner == PNOR_OWNER_HOST) { + reg = PV_OCC_GP0_OR; + mask = PV_OCC_GP0_PNOR_OWNER; + } else { + reg = PV_OCC_GP0_AND; + mask = ~PV_OCC_GP0_PNOR_OWNER; + } + + xscom_write(chip_id, reg, mask); +} + +void occ_pnor_set_owner(enum pnor_owner owner) +{ + struct proc_chip *chip; + + for_each_chip(chip) + occ_pnor_set_one_owner(chip->id, owner); +} + static bool fsp_occ_msg(u32 cmd_sub_mod, struct fsp_msg *msg) { u32 dbob_id, seq_id; diff --git a/include/skiboot.h b/include/skiboot.h index beaa7db..0fe50e9 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -221,6 +221,13 @@ extern void occ_send_dummy_interrupt(void); /* OCC load support */ extern void occ_poke_load_queue(void); +/* OCC/Host PNOR ownership */ +enum pnor_owner { + PNOR_OWNER_HOST, + PNOR_OWNER_EXTERNAL, +}; +extern void occ_pnor_set_owner(enum pnor_owner owner); + /* PRD */ extern void prd_psi_interrupt(uint32_t proc); extern void prd_tmgt_interrupt(uint32_t proc);