| Message ID | 20211108150554.4457-2-conor.dooley@microchip.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Update the icicle kit device tree | expand |
Am Montag, 8. November 2021, 16:05:42 CET schrieb conor.dooley@microchip.com: > From: Ivan Griffin <ivan.griffin@microchip.com> > > Provide named identifiers for device tree for RISC-V interrupts. > > Licensed under GPL and MIT, as this file may be useful to any OS that > uses device tree. > > Signed-off-by: Ivan Griffin <ivan.griffin@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h > > diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h > new file mode 100644 > index 000000000000..e1c32f6090ac > --- /dev/null > +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* > + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H > +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H > + > +#define HART_INT_U_SOFT 0 > +#define HART_INT_S_SOFT 1 > +#define HART_INT_M_SOFT 3 > +#define HART_INT_U_TIMER 4 > +#define HART_INT_S_TIMER 5 > +#define HART_INT_M_TIMER 7 > +#define HART_INT_U_EXT 8 > +#define HART_INT_S_EXT 9 > +#define HART_INT_M_EXT 11 (1) From checking clic doc [0] I see an additional 12 CLIC software interrupt defined. (2) The doc states that the ordering is a recommendation and "not mandatory in all incarnations of the CLIC" Is that clarified somewhere else that this more than recommended? Thanks Heiko [0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc > + > +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ >
On Tue, Nov 23, 2021 at 4:38 PM Heiko Stübner <heiko@sntech.de> wrote: > > Am Montag, 8. November 2021, 16:05:42 CET schrieb conor.dooley@microchip.com: > > From: Ivan Griffin <ivan.griffin@microchip.com> > > > > Provide named identifiers for device tree for RISC-V interrupts. > > > > Licensed under GPL and MIT, as this file may be useful to any OS that > > uses device tree. > > > > Signed-off-by: Ivan Griffin <ivan.griffin@microchip.com> > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h > > > > diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h > > new file mode 100644 > > index 000000000000..e1c32f6090ac > > --- /dev/null > > +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h > > @@ -0,0 +1,19 @@ > > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > > +/* > > + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved. > > + */ > > + > > +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H > > +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H > > + > > +#define HART_INT_U_SOFT 0 > > +#define HART_INT_S_SOFT 1 > > +#define HART_INT_M_SOFT 3 > > +#define HART_INT_U_TIMER 4 > > +#define HART_INT_S_TIMER 5 > > +#define HART_INT_M_TIMER 7 > > +#define HART_INT_U_EXT 8 > > +#define HART_INT_S_EXT 9 > > +#define HART_INT_M_EXT 11 > > (1) From checking clic doc [0] I see an additional > 12 CLIC software interrupt > defined. Local IRQ #12 is for S-mode guest external interrupts as-per the ratified H-extension specification. I guess CLIC spec needs to be updated. Regards, Anup > > (2) The doc states that the ordering is a recommendation and > "not mandatory in all incarnations of the CLIC" > Is that clarified somewhere else that this more than recommended? > > Thanks > Heiko > > > [0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc > > > + > > +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ > > > > > >
On Mon, 08 Nov 2021 15:05:42 +0000, conor.dooley@microchip.com wrote: > From: Ivan Griffin <ivan.griffin@microchip.com> > > Provide named identifiers for device tree for RISC-V interrupts. > > Licensed under GPL and MIT, as this file may be useful to any OS that > uses device tree. > > Signed-off-by: Ivan Griffin <ivan.griffin@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h new file mode 100644 index 000000000000..e1c32f6090ac --- /dev/null +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H + +#define HART_INT_U_SOFT 0 +#define HART_INT_S_SOFT 1 +#define HART_INT_M_SOFT 3 +#define HART_INT_U_TIMER 4 +#define HART_INT_S_TIMER 5 +#define HART_INT_M_TIMER 7 +#define HART_INT_U_EXT 8 +#define HART_INT_S_EXT 9 +#define HART_INT_M_EXT 11 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */