From patchwork Fri Apr 25 09:31:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 342728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-ve0-f188.google.com (mail-ve0-f188.google.com [209.85.128.188]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 38169141A2E for ; Fri, 25 Apr 2014 19:31:26 +1000 (EST) Received: by mail-ve0-f188.google.com with SMTP id db12sf708076veb.5 for ; Fri, 25 Apr 2014 02:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=20120806; h=mime-version:from:to:cc:subject:date:message-id:in-reply-to :references:x-original-sender:x-original-authentication-results :reply-to:precedence:mailing-list:list-id:list-post:list-help :list-archive:sender:list-subscribe:list-unsubscribe:content-type; bh=faCVYMx2AZGh1Fu7//m/ERuML2nRbn2Cc7jRd1uryrs=; b=RnPUwZzwZGpwW3VXJjreNejNPNECsux8VJB9eNdqGQoww7n5CxJlHiSFAFilgWIzuD 4lB+06jiFsT7UsQTsyTfh6VTEfFL0uWf7mGagU02i3+K/PCzWWUa07rKsIlA41425ozZ 7TKoErOvyrTvP23rq/zV1634BqSAOf38btFF9R1cXZ8ibFFWyeZ8GOlwtE9VJShKt5rU 0lwagy4nF9gqNsdOWg0a4cTJZ68NXDdaQ/xHozDJyt/cBVVGSKgsV/5+in3+sZOGQy7P a7U/bW1s300Xdk7M3FJWh5tS64YlmhuopG7IboPY5GqpO+Wu8BUi6dFk+6klhPIHQi0s L5HQ== X-Received: by 10.140.44.75 with SMTP id f69mr21317qga.11.1398418282914; Fri, 25 Apr 2014 02:31:22 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: rtc-linux@googlegroups.com Received: by 10.140.23.106 with SMTP id 97ls1506513qgo.34.gmail; Fri, 25 Apr 2014 02:31:22 -0700 (PDT) X-Received: by 10.224.95.9 with SMTP id b9mr3919799qan.2.1398418282548; Fri, 25 Apr 2014 02:31:22 -0700 (PDT) Received: from collaborate-mta1.arm.com (fw-tnat.austin.arm.com. [217.140.110.23]) by gmr-mx.google.com with ESMTP id zs4si2591576pbc.1.2014.04.25.02.31.22 for ; Fri, 25 Apr 2014 02:31:22 -0700 (PDT) Received-SPF: pass (google.com: domain of marc.zyngier@arm.com designates 217.140.110.23 as permitted sender) client-ip=217.140.110.23; Received: from e102391-lin.cambridge.arm.com (e102391-lin.cambridge.arm.com [10.1.209.166]) by collaborate-mta1.arm.com (Postfix) with ESMTP id 5205A13FCB5; Fri, 25 Apr 2014 04:31:21 -0500 (CDT) From: Marc Zyngier To: linux-kernel@vger.kernel.org, rtc-linux@googlegroups.com Cc: Russell King , Will Deacon , Catalin Marinas , Alessandro Zummo Subject: [rtc-linux] [PATCH 5/7] rtc-cmos: implement driver private locking Date: Fri, 25 Apr 2014 10:31:13 +0100 Message-Id: <1398418275-9671-6-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1398418275-9671-1-git-send-email-marc.zyngier@arm.com> References: <1398418275-9671-1-git-send-email-marc.zyngier@arm.com> X-Original-Sender: marc.zyngier@arm.com X-Original-Authentication-Results: gmr-mx.google.com; spf=pass (google.com: domain of marc.zyngier@arm.com designates 217.140.110.23 as permitted sender) smtp.mail=marc.zyngier@arm.com Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: Sender: rtc-linux@googlegroups.com List-Subscribe: , List-Unsubscribe: , A number of architecture happen to share a lock between the rtc-cmos driver and the core architectural code for good reasons (or at least, reasons that matter to the architecture). Other architectures don't do that, but still have to define a lock that is only used by the RTC driver. How annoying! Implement a set of driver private locking primitives, and expose a config option allowing the architecture to select it if it doesn't require to share the lock with the RTC driver. Signed-off-by: Marc Zyngier --- drivers/rtc/Kconfig | 3 +++ drivers/rtc/rtc-cmos.c | 16 ++++++++++++++++ include/asm-generic/rtc.h | 5 +++++ 3 files changed, 24 insertions(+) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 10974f7..12bc27d 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -684,6 +684,9 @@ config RTC_DRV_CMOS_MMIO_STRICT select RTC_DRV_CMOS_MMIO bool +config RTC_DRV_CMOS_PRIV_LOCK + bool + config RTC_DRV_ALPHA bool "Alpha PC-style CMOS" depends on ALPHA diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index e2d1338..eb5d05c 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -107,6 +107,22 @@ static inline void rtc_cmos_set_base(void __iomem *base) static void rtc_cmos_set_base(void __iomem *base) {} #endif +#ifdef CONFIG_RTC_DRV_CMOS_PRIV_LOCK +static DEFINE_SPINLOCK(rtc_private_lock); + +static unsigned long rtc_cmos_lock(void) +{ + unsigned long flags; + spin_lock_irqsave(&rtc_private_lock, flags); + return flags; +} + +static void rtc_cmos_unlock(unsigned long flags) +{ + spin_unlock_irqrestore(&rtc_private_lock, flags); +} +#endif + /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; * always mask it against the irq enable bits in RTC_CONTROL. Bit values * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. diff --git a/include/asm-generic/rtc.h b/include/asm-generic/rtc.h index 236693b..1d21408 100644 --- a/include/asm-generic/rtc.h +++ b/include/asm-generic/rtc.h @@ -43,6 +43,10 @@ static inline void do_cmos_write(u8 val, u8 reg) } #endif +#ifdef CONFIG_RTC_DRV_CMOS_PRIV_LOCK +static unsigned long rtc_cmos_lock(void); +static void rtc_cmos_unlock(unsigned long flags); +#else static inline unsigned long rtc_cmos_lock(void) { unsigned long flags; @@ -54,6 +58,7 @@ static inline void rtc_cmos_unlock(unsigned long flags) { spin_unlock_irqrestore(&rtc_lock, flags); } +#endif /* * Returns true if a clock update is in progress