diff mbox series

[v2,13/24] target/hexagon: convert raise_exception to hexagon_raise_exception

Message ID 20260928052051.251-14-luoyonggang@gmail.com
State New
Headers show
Series accel/tcg: share raise_excp across TCG targets | expand

Commit Message

Yonggang Luo Sept. 28, 2026, 5:20 a.m. UTC 
Fold C do_raise_exception into hexagon_raise_exception_err with
vaddr pc and a retaddr parameter, and exit via cpu_loop_exit_excp.
Prefix leftover TCG raise_exception to hexagon_raise_exception so
translate keeps the CPU_LOG_INT log and ASSERT_DIRECT_TO_GUEST_UNSET.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
---
 target/hexagon/cpu.c       | 13 +++++++------
 target/hexagon/cpu.h       |  2 +-
 target/hexagon/helper.h    |  3 ++-
 target/hexagon/internal.h  |  5 -----
 target/hexagon/macros.h    |  2 +-
 target/hexagon/op_helper.c | 29 +++++++++++------------------
 target/hexagon/translate.c | 11 ++++++-----
 7 files changed, 28 insertions(+), 37 deletions(-)
diff mbox series

Patch

diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 1f7d8a8df70..3739f3f4561 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -342,7 +342,7 @@  static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs)
     }
     if (pc & PCALIGN_MASK) {
         env->cause_code = HEX_CAUSE_PC_NOT_ALIGNED;
-        hexagon_raise_exception_err(env, HEX_EVENT_PRECISE, pc);
+        hexagon_raise_exception_err(env, HEX_EVENT_PRECISE, pc, 0);
     }
 
 #ifndef CONFIG_USER_ONLY
@@ -734,14 +734,15 @@  static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
             return false;
         }
         raise_perm_exception(cs, address, slot, access_type, excp);
-        do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],
-                           retaddr);
+        hexagon_raise_exception_err(env, cs->exception_index,
+                                    env->gpr[HEX_REG_PC], retaddr);
     }
     if (probe) {
         return false;
     }
     raise_tlbmiss_exception(cs, address, slot, access_type);
-    do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC], retaddr);
+    hexagon_raise_exception_err(env, cs->exception_index,
+                                env->gpr[HEX_REG_PC], retaddr);
 }
 
 #include "hw/core/sysemu-cpu-ops.h"
@@ -784,8 +785,8 @@  void hexagon_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
     CPUHexagonState *env = cpu_env(cs);
 
     raise_misaligned_exception(cs, addr, 0, access_type);
-    do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],
-                       retaddr);
+    hexagon_raise_exception_err(env, cs->exception_index,
+                                env->gpr[HEX_REG_PC], retaddr);
 }
 
 #endif
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index df4c0182247..1edcc3ef6c3 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -232,7 +232,7 @@  FIELD(TB_FLAGS, HVX_COPROC_ENABLED, 5, 1)
 
 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
                                             uint32_t exception,
-                                            uintptr_t pc);
+                                            vaddr pc, uintptr_t retaddr);
 
 #ifndef CONFIG_USER_ONLY
 /*
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 71c8da4c46d..6cd63f631b7 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -18,7 +18,8 @@ 
 #include "internal.h"
 #include "helper_protos_generated.h.inc"
 
-DEF_HELPER_FLAGS_3(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32, i32)
+DEF_HELPER_FLAGS_3(hexagon_raise_exception, TCG_CALL_NO_RETURN, noreturn,
+                   env, i32, vaddr)
 DEF_HELPER_2(commit_store, void, env, int)
 DEF_HELPER_3(gather_store, void, env, i32, int)
 DEF_HELPER_1(commit_hvx_stores, void, env)
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index 05d1129916e..4b7a784fbc7 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -36,11 +36,6 @@  extern const char * const hexagon_sregnames[];
 extern const char * const hexagon_gregnames[];
 #endif
 
-void G_NORETURN do_raise_exception(CPUHexagonState *env,
-        uint32_t exception,
-        uint32_t PC,
-        uintptr_t retaddr);
-
 #define hexagon_cpu_mmu_enabled(env) ({ \
     HexagonCPU *cpu = env_archcpu(env); \
     cpu->globalregs ? \
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index a5b9c24c6bb..4a87f6d72f1 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -637,7 +637,7 @@  static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 #ifdef CONFIG_USER_ONLY
 #define fTRAP(TRAPTYPE, IMM) \
     do { \
-        hexagon_raise_exception_err(env, HEX_EVENT_TRAP0, PC); \
+        hexagon_raise_exception_err(env, HEX_EVENT_TRAP0, PC, 0); \
     } while (0)
 #endif
 
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 4f00ca773f3..dfdb597f3fc 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -72,31 +72,24 @@  uint64_t HELPER(utimer)(void)
 #define SF_MANTBITS    23
 
 /* Exceptions processing helpers */
-G_NORETURN
-void do_raise_exception(CPUHexagonState *env, uint32_t exception,
-                        uint32_t PC, uintptr_t retaddr)
+G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
+                                            uint32_t exception,
+                                            vaddr pc, uintptr_t retaddr)
 {
     CPUState *cs = env_cpu(env);
-    qemu_log_mask(CPU_LOG_INT, "%s: 0x%08" PRIx32 ", @ %08" PRIx32 "\n",
-                  __func__, exception, PC);
+    qemu_log_mask(CPU_LOG_INT, "%s: 0x%08" PRIx32 ", @ %08" VADDR_PRIx "\n",
+                  __func__, exception, pc);
     ASSERT_DIRECT_TO_GUEST_UNSET(env, exception);
 
-    env->gpr[HEX_REG_PC] = PC;
-    cs->exception_index = exception;
-    cpu_loop_exit_restore(cs, retaddr);
-}
-
-G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
-                                            uint32_t exception,
-                                            uintptr_t pc)
-{
-    do_raise_exception(env, exception, pc, 0);
+    env->gpr[HEX_REG_PC] = pc;
+    cpu_loop_exit_excp(cs, exception, retaddr);
 }
 
-G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp,
-                                        uint32_t PC)
+G_NORETURN void HELPER(hexagon_raise_exception)(CPUHexagonState *env,
+                                                uint32_t exception,
+                                                vaddr pc)
 {
-    hexagon_raise_exception_err(env, excp, PC);
+    hexagon_raise_exception_err(env, exception, pc, 0);
 }
 
 void log_store32(CPUHexagonState *env, target_ulong addr,
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 827859e052c..3bef721d7d8 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -138,11 +138,12 @@  intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
     return offset;
 }
 
-static void gen_precise_exception(int cause, uint32_t PC)
+static void gen_precise_exception(int cause, vaddr pc)
 {
     tcg_gen_movi_i32(hex_cause_code, cause);
-    gen_helper_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE),
-                               tcg_constant_i32(PC));
+    gen_helper_hexagon_raise_exception(tcg_env,
+                                       tcg_constant_i32(HEX_EVENT_PRECISE),
+                                       tcg_constant_vaddr(pc));
 }
 
 #ifndef CONFIG_USER_ONLY
@@ -1139,11 +1140,11 @@  static void update_exec_counters(DisasContext *ctx)
  */
 static void check_imprecise_exception(DisasContext *ctx)
 {
-    TCGv PC = tcg_constant_tl(ctx->pkt.pc);
     TCGLabel *label = gen_new_label();
 
     tcg_gen_brcondi_tl(TCG_COND_EQ, hex_imprecise_exception, 0, label);
-    gen_helper_raise_exception(tcg_env, hex_imprecise_exception, PC);
+    gen_helper_hexagon_raise_exception(tcg_env, hex_imprecise_exception,
+                                       tcg_constant_vaddr(ctx->pkt.pc));
     gen_set_label(label);
 }
 #endif