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envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state(). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 11 ----------- target/mips/tcg/tcg-internal.h | 2 ++ target/mips/cpu.c | 1 + target/mips/tcg/translate.c | 9 +++++++++ 4 files changed, 12 insertions(+), 11 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index caa12a2dd3..9d2f7e0194 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1362,17 +1362,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); -#define TARGET_HAS_CPU_GET_TB_CPU_STATE - -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->active_tc.PC; - *cs_base = 0; - *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index aef032c48d..c54d5c64b2 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -24,6 +24,8 @@ G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, void mips_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data); +void mips_get_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); const char *mips_exception_name(int32_t exception); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8d8f690a53..6cc64b7628 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -551,6 +551,7 @@ static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, + .get_cpu_state = mips_get_cpu_state, #if !defined(CONFIG_USER_ONLY) .tlb_fill = mips_cpu_tlb_fill, diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 06c108cc9c..4ecac13a8f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15581,3 +15581,12 @@ void mips_restore_state_to_opc(CPUState *cs, break; } } + +void mips_get_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->active_tc.PC; + *cs_base = 0; + *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +}