From patchwork Mon Jun 1 18:04:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 479129 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0A753140DCC for ; Tue, 2 Jun 2015 04:07:20 +1000 (AEST) Received: from localhost ([::1]:53750 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU7J-0007xU-RT for incoming@patchwork.ozlabs.org; Mon, 01 Jun 2015 14:07:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4o-0003I5-DT for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzU4i-0008Hp-Vn for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:42 -0400 Received: from mail-ob0-f180.google.com ([209.85.214.180]:36454) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4i-0008Hi-RG for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:36 -0400 Received: by obbea2 with SMTP id ea2so109630422obb.3 for ; Mon, 01 Jun 2015 11:04:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=iQGyXc/ucmhEujVq6JdS0w76l7ww/3uVZcKOWhOG3gs=; b=DNamxs3eN6LDJkGzFcwdM90iElVqrKLLm0Q367PkRcsnOzoGSHYD3D8E6azgewIkfv LZuPBF/5UnxAnsVaD1QHMgHUbCsmkvNL61RKGywLiJYigbKIQbMSZMTCwspyViiJEu1r Xh8vOJQNX0qUIYLpDLd9HNdc8jWO6RR9icoA57Zc0w45sHZdTI0K/HF2x7twwVTNJxme ii9WXwRN5VCGE0O3lKZApi3Bd/cUZCfHquJWfHOX8rucf/yiy63zMv8vjZ7VT8ATydy2 9p7EJTe3u+iT+HNhuiOH4kOXBQ2BqodPs6pnHXE47OPBQmqff8RXQEkuzWjw76Fp5qoZ bdGQ== X-Gm-Message-State: ALoCoQlewUtCGzK6WP+RVwu5YoxkKnRG2BIPESEKGA+070+gjYfOaIE9H25dgK0aNsnxGEsV/A/m X-Received: by 10.183.1.41 with SMTP id bd9mr18789350obd.14.1433181876270; Mon, 01 Jun 2015 11:04:36 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id a194sm8023533oih.2.2015.06.01.11.04.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Jun 2015 11:04:35 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 1 Jun 2015 11:04:34 -0700 Message-Id: X-Mailer: git-send-email 2.4.2.3.g2ffcb72 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.180 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v1 8/9] arm: xlnx-zynqmp: Preface CPU variables with "A" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The CPUs currently supported by zynqmp are the APU (application processing unit) CPUs. There are other CPUs in Zynqmp so unqualified "cpus" in ambiguous. Preface the variables with "A" accordingly, to prepare support adding the RPU (realtime processing unit) processors. Signed-off-by: Peter Crosthwaite --- hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 24 ++++++++++++------------ include/hw/arm/xlnx-zynqmp.h | 4 ++-- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c index b924f5e..1893b9f 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-ep108.c @@ -65,7 +65,7 @@ static void xlnx_ep108_init(MachineState *machine) xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline; xlnx_ep108_binfo.initrd_filename = machine->initrd_filename; xlnx_ep108_binfo.loader_start = 0; - arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo); + arm_load_kernel(&s->soc.acpu[0], &xlnx_ep108_binfo); } static QEMUMachine xlnx_ep108_machine = { diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 6b01965..6faa578 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -64,10 +64,10 @@ static void xlnx_zynqmp_init(Object *obj) XlnxZynqMPState *s = XLNX_ZYNQMP(obj); int i; - for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { - object_initialize(&s->cpu[i], sizeof(s->cpu[i]), + for (i = 0; i < XLNX_ZYNQMP_NUM_ACPUS; i++) { + object_initialize(&s->acpu[i], sizeof(s->acpu[i]), "cortex-a53-" TYPE_ARM_CPU); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), + object_property_add_child(obj, "acpu[*]", OBJECT(&s->acpu[i]), &error_abort); } @@ -95,7 +95,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); - qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_ACPUS); object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err) { error_propagate((errp), (err)); @@ -121,38 +121,38 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } } - for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { + for (i = 0; i < XLNX_ZYNQMP_NUM_ACPUS; i++) { qemu_irq irq; - object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, + object_property_set_int(OBJECT(&s->acpu[i]), QEMU_PSCI_CONDUIT_SMC, "psci-conduit", &error_abort); if (i > 0) { /* Secondary CPUs start in PSCI powered-down state */ - object_property_set_bool(OBJECT(&s->cpu[i]), true, + object_property_set_bool(OBJECT(&s->acpu[i]), true, "start-powered-off", &error_abort); } - object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR, + object_property_set_int(OBJECT(&s->acpu[i]), GIC_BASE_ADDR, "reset-cbar", &err); if (err) { error_propagate((errp), (err)); return; } - object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); + object_property_set_bool(OBJECT(&s->acpu[i]), true, "realized", &err); if (err) { error_propagate((errp), (err)); return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(&s->acpu[i]), ARM_CPU_IRQ)); irq = qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq); + qdev_connect_gpio_out(DEVICE(&s->acpu[i]), 0, irq); irq = qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq); + qdev_connect_gpio_out(DEVICE(&s->acpu[i]), 1, irq); } for (i = 0; i < GIC_NUM_SPI_INTR; i++) { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 79c2b0b..bb67ef6 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -27,7 +27,7 @@ #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ TYPE_XLNX_ZYNQMP) -#define XLNX_ZYNQMP_NUM_CPUS 4 +#define XLNX_ZYNQMP_NUM_ACPUS 4 #define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_NUM_UARTS 2 @@ -47,7 +47,7 @@ typedef struct XlnxZynqMPState { DeviceState parent_obj; /*< public >*/ - ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS]; + ARMCPU acpu[XLNX_ZYNQMP_NUM_ACPUS]; GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];