From patchwork Sat Sep 15 09:50:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 970344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nocrew.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CypX6cp5z9sBJ for ; Mon, 17 Sep 2018 04:44:20 +1000 (AEST) Received: from localhost ([::1]:59910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1c1q-0005p3-Gi for incoming@patchwork.ozlabs.org; Sun, 16 Sep 2018 14:44:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1bwo-0002f2-A6 for qemu-devel@nongnu.org; Sun, 16 Sep 2018 14:39:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1bwl-0005YF-4E for qemu-devel@nongnu.org; Sun, 16 Sep 2018 14:39:06 -0400 Received: from ste-pvt-msa1.bahnhof.se ([213.80.101.70]:50797) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g1bwk-0005TV-On for qemu-devel@nongnu.org; Sun, 16 Sep 2018 14:39:03 -0400 Received: from localhost (localhost [127.0.0.1]) by ste-pvt-msa1.bahnhof.se (Postfix) with ESMTP id B7D053FDF9; Sun, 16 Sep 2018 20:38:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): Cc: ....maydell@linaro.org>, \n \tJ\303\203\302\274rgen Urban In-Reply-To: References: <4b72263c848ecf76a06f973294cc5b5b67fe4080.1537122775.git.noring@nocrew.org> <842278e9826c21da2a425feea040657af70a59cd.1537122775.git.noring@nocrew.org> From: Fredrik Noring Date: Sat, 15 Sep 2018 11:50:32 +0200 To: Aleksandar Markovic , "Maciej W. Rozycki" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 213.80.101.70 Subject: [Qemu-devel] [PATCH v4 6/8] target/mips: Define the R5900 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-devel@nongnu.org, J??rgen Urban , Petar Jovanovic , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The primary purpose of this change is to support programs compiled by GCC for the R5900 target and thereby run R5900 Linux distributions, for example Gentoo. In particular, this avoids issues with cross compilation. This change has been tested with Gentoo compiled for R5900, including native compilation of several packages under QEMU. Signed-off-by: Fredrik Noring --- target/mips/translate_init.inc.c | 47 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index b3320b9dc7..71fd83de06 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -410,6 +410,53 @@ const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R5 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, + { + .name = "R5900", + .CP0_PRid = 0x00003800, + /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */ + .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0), + .CP0_Status_rw_bitmask = 0xF4C79C1F, +#ifdef CONFIG_USER_ONLY + /* + * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC + * emulation. For user only, QEMU is the kernel, so we emulate the traps + * by simply emulating the instructions directly. + * + * Note: Config1 is only used internally, the R5900 has only Config0. + */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, + .CP0_LLAddr_shift = 4, + .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0x0183FFFF, +#else + /* + * The R5900 COP1 FPU implements single-precision floating-point + * operations but is not entirely IEEE 754-1985 compatible. In + * particular, + * + * - NaN (not a number) and plus/minus infinities are not supported; + * - exception mechanisms are not fully supported; + * - denormalized numbers are not supported; + * - rounding towards nearest and plus/minus infinities are not supported; + * - computed results usually differs in the least significant bit; + * - saturating instructions can differ more than the least significant bit. + * + * Since only rounding towards zero is supported, the two least + * significant bits of FCR31 are hardwired to 01. + * + * FPU emulation is disabled here until it is implemented. + * + * Note: Config1 is only used internally, the R5900 has only Config0. + */ + .CP0_Config1 = (47 << CP0C1_MMU), +#endif /* !CONFIG_USER_ONLY */ + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_R5900, + .mmu_type = MMU_TYPE_R4000, + }, { /* A generic CPU supporting MIPS32 Release 6 ISA. FIXME: Support IEEE 754-2008 FP.