From patchwork Thu Aug 27 23:15:11 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juan Quintela X-Patchwork-Id: 32314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id 074B8B7BE7 for ; Fri, 28 Aug 2009 09:56:50 +1000 (EST) Received: from localhost ([127.0.0.1]:49086 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mgopi-0000cA-Dq for incoming@patchwork.ozlabs.org; Thu, 27 Aug 2009 19:56:46 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MgopD-0000aG-Ps for qemu-devel@nongnu.org; Thu, 27 Aug 2009 19:56:15 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Mgop9-0000Ub-6l for qemu-devel@nongnu.org; Thu, 27 Aug 2009 19:56:15 -0400 Received: from [199.232.76.173] (port=46634 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mgop9-0000UP-4e for qemu-devel@nongnu.org; Thu, 27 Aug 2009 19:56:11 -0400 Received: from mx1.redhat.com ([209.132.183.28]:25006) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Mgokl-0003wx-T3 for qemu-devel@nongnu.org; Thu, 27 Aug 2009 19:51:40 -0400 Received: from int-mx03.intmail.prod.int.phx2.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.16]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n7RNHppL010821 for ; Thu, 27 Aug 2009 19:17:51 -0400 Received: from localhost.localdomain (vpn1-4-202.ams2.redhat.com [10.36.4.202]) by int-mx03.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id n7RNHetw031343; Thu, 27 Aug 2009 19:17:49 -0400 From: Juan Quintela To: qemu-devel@nongnu.org Date: Fri, 28 Aug 2009 01:15:11 +0200 Message-Id: In-Reply-To: References: In-Reply-To: References: X-Scanned-By: MIMEDefang 2.67 on 10.5.11.16 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Subject: [Qemu-devel] [PATCH 07/13] Create PIIX3State instead of using PCIDevice for PIIX3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Juan Quintela --- hw/piix_pci.c | 23 ++++++++++++++--------- 1 files changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 4739604..29bd92c 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -33,6 +33,10 @@ typedef uint32_t pci_addr_t; typedef PCIHostState I440FXState; +typedef struct PIIX3State { + PCIDevice dev; +} PIIX3State; + struct PCII440FXState { PCIDevice dev; target_phys_addr_t isa_page_descs[384 / 4]; @@ -229,7 +233,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic) /* PIIX3 PCI to ISA bridge */ -static PCIDevice *piix3_dev; +static PIIX3State *piix3_dev; static void piix3_set_irq(void *opaque, int irq_num, int level) { @@ -240,13 +244,13 @@ static void piix3_set_irq(void *opaque, int irq_num, int level) /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = piix3_dev->config[0x60 + irq_num]; + pic_irq = piix3_dev->dev.config[0x60 + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix3_dev->config[0x60 + i]) + if (pic_irq == piix3_dev->dev.config[0x60 + i]) pic_level |= pci_irq_levels[i]; } qemu_set_irq(pic[pic_irq], pic_level); @@ -255,8 +259,8 @@ static void piix3_set_irq(void *opaque, int irq_num, int level) static void piix3_reset(void *opaque) { - PCIDevice *d = opaque; - uint8_t *pci_conf = d->config; + PIIX3State *d = opaque; + uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; // master, memory and I/O pci_conf[0x05] = 0x00; @@ -307,14 +311,15 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id) return pci_device_load(d, f); } -static void piix3_initfn(PCIDevice *d) +static void piix3_initfn(PCIDevice *dev) { + PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); uint8_t *pci_conf; - isa_bus_new(&d->qdev); + isa_bus_new(&d->dev.qdev); register_savevm("PIIX3", 0, 2, piix_save, piix_load, d); - pci_conf = d->config; + pci_conf = d->dev.config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); @@ -345,7 +350,7 @@ static PCIDeviceInfo i440fx_info[] = { },{ .qdev.name = "PIIX3", .qdev.desc = "ISA bridge", - .qdev.size = sizeof(PCIDevice), + .qdev.size = sizeof(PIIX3State), .qdev.no_user = 1, .init = piix3_initfn, },{