From patchwork Fri Jul 3 09:38:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhu Guihua X-Patchwork-Id: 490963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 75823140777 for ; Fri, 3 Jul 2015 19:41:07 +1000 (AEST) Received: from localhost ([::1]:40070 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAxSx-0002ry-Ce for incoming@patchwork.ozlabs.org; Fri, 03 Jul 2015 05:41:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAxSJ-0001yV-IU for qemu-devel@nongnu.org; Fri, 03 Jul 2015 05:40:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZAxSG-00084G-Ad for qemu-devel@nongnu.org; Fri, 03 Jul 2015 05:40:23 -0400 Received: from [59.151.112.132] (port=22910 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAxSE-00081A-CI for qemu-devel@nongnu.org; Fri, 03 Jul 2015 05:40:20 -0400 X-IronPort-AV: E=Sophos;i="5.13,665,1427731200"; d="scan'208";a="98053839" Received: from unknown (HELO edo.cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 03 Jul 2015 17:44:07 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (localhost.localdomain [127.0.0.1]) by edo.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id t639cUCD010620; Fri, 3 Jul 2015 17:38:30 +0800 Received: from G08FNSTD140041.g08.fujitsu.local (10.167.226.252) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.181.6; Fri, 3 Jul 2015 17:40:09 +0800 From: Zhu Guihua To: , , , , Date: Fri, 3 Jul 2015 17:38:56 +0800 Message-ID: X-Mailer: git-send-email 1.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.226.252] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Cc: chen.fan.fnst@cn.fujitsu.com, izumi.taku@jp.fujitsu.com, Zhu Guihua Subject: [Qemu-devel] [PATCH v9 1/4] apic: map APIC's MMIO region at each CPU's address space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Fan Replace mapping APIC at global system address space with mapping it at per-CPU address spaces. Signed-off-by: Chen Fan Signed-off-by: Zhu Guihua --- hw/i386/pc.c | 7 ------- hw/intc/apic_common.c | 6 ------ target-i386/cpu.c | 21 +++++++++++++++++++++ 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7072930..9f16128 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1076,13 +1076,6 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) object_unref(OBJECT(cpu)); } - /* map APIC MMIO area if CPU has APIC */ - if (cpu && cpu->apic_state) { - /* XXX: what if the base changes? */ - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, - APIC_DEFAULT_ADDRESS, 0x1000); - } - /* tell smbios about cpuid version and features */ smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); } diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 0032b97..c0b32eb 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -296,7 +296,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp) APICCommonClass *info; static DeviceState *vapic; static int apic_no; - static bool mmio_registered; if (apic_no >= MAX_APICS) { error_setg(errp, "%s initialization failed.", @@ -307,11 +306,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp) info = APIC_COMMON_GET_CLASS(s); info->realize(dev, errp); - if (!mmio_registered) { - ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev)); - memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory); - mmio_registered = true; - } /* Note: We need at least 1M to map the VAPIC option ROM */ if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 36b07f9..11affce 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2741,6 +2741,7 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) /* TODO: convert to link<> */ apic = APIC_COMMON(cpu->apic_state); apic->cpu = cpu; + apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; } static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) @@ -2785,8 +2786,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) X86CPU *cpu = X86_CPU(dev); X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); CPUX86State *env = &cpu->env; + APICCommonState *apic; Error *local_err = NULL; static bool ht_warned; + static bool apic_mmio_map_once; if (cpu->apic_id < 0) { error_setg(errp, "apic-id property was not initialized properly"); @@ -2873,6 +2876,24 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) if (local_err != NULL) { goto out; } + + /* map APIC MMIO area */ + apic = APIC_COMMON(cpu->apic_state); + if (tcg_enabled()) { + memory_region_add_subregion_overlap(cpu->cpu_as_root, + apic->apicbase & + MSR_IA32_APICBASE_BASE, + &apic->io_memory, + 0x1000); + } else if (!apic_mmio_map_once) { + memory_region_add_subregion_overlap(get_system_memory(), + apic->apicbase & + MSR_IA32_APICBASE_BASE, + &apic->io_memory, + 0x1000); + apic_mmio_map_once = true; + } + cpu_reset(cs); xcc->parent_realize(dev, &local_err);