From patchwork Wed Nov 7 19:18:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 994455 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nocrew.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42qx7S5Y2Pz9s8r for ; Thu, 8 Nov 2018 06:19:48 +1100 (AEDT) Received: from localhost ([::1]:50382 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKTMg-0006NH-7j for incoming@patchwork.ozlabs.org; Wed, 07 Nov 2018 14:19:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKTM1-0006Jj-P1 for qemu-devel@nongnu.org; Wed, 07 Nov 2018 14:19:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKTLy-0004zQ-N6 for qemu-devel@nongnu.org; Wed, 07 Nov 2018 14:19:05 -0500 Received: from pio-pvt-msa2.bahnhof.se ([79.136.2.41]:50445) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKTLy-0004yP-7G for qemu-devel@nongnu.org; Wed, 07 Nov 2018 14:19:02 -0500 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTP id A4D7F3F6FD; Wed, 7 Nov 2018 20:19:00 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at bahnhof.se Received: from pio-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rKepASdUUsn8; Wed, 7 Nov 2018 20:18:55 +0100 (CET) Received: from localhost (h-41-252.A163.priv.bahnhof.se [46.59.41.252]) (Authenticated sender: mb547485) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id 64DAA3F6B6; Wed, 7 Nov 2018 20:18:55 +0100 (CET) Date: Wed, 7 Nov 2018 20:18:55 +0100 From: Fredrik Noring To: Aleksandar Markovic , Aurelien Jarno , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= , Richard Henderson Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.41 Subject: [Qemu-devel] [PATCH v2 3/6] target/mips: Fix HI[ac] and LO[ac] 32-bit truncation with MIPS64 DSP ASE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?J=C3=BCrgen?= Urban , Jia Liu , "Maciej W. Rozycki" , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This change removes the 32-bit truncation of the HI[ac] and LO[ac] special purpose registers when ac range from 1 to 3 for the instructions MFHI, MFLO, MTHI and MTLO. The "MIPS Architecture for Programmers Volume IV-e: MIPS DSP Module for MIPS64 Architecture" manual specifies that all 64 bits are copied in all cases: MFHI: GPR[rd]63..0 <- HI[ac]63..0 MFLO: GPR[rd]63..0 <- LO[ac]63..0 MTHI: HI[ac]63..0 <- GPR[rs]63..0 MTLO: LO[ac]63..0 <- GPR[rs]63..0 Fixes: 4133498f8e53 ("Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number") Cc: Jia Liu Reported-by: Maciej W. Rozycki Signed-off-by: Fredrik Noring --- target/mips/translate.c | 36 ++++-------------------------------- 1 file changed, 4 insertions(+), 32 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3ddd70043a..19ae7d2f1c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4409,49 +4409,21 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) switch (opc) { case OPC_MFHI: -#if defined(TARGET_MIPS64) - if (acc != 0) { - tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); - } else -#endif - { - tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); - } + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); break; case OPC_MFLO: -#if defined(TARGET_MIPS64) - if (acc != 0) { - tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); - } else -#endif - { - tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); - } + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); break; case OPC_MTHI: if (reg != 0) { -#if defined(TARGET_MIPS64) - if (acc != 0) { - tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]); - } else -#endif - { - tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); - } + tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); } else { tcg_gen_movi_tl(cpu_HI[acc], 0); } break; case OPC_MTLO: if (reg != 0) { -#if defined(TARGET_MIPS64) - if (acc != 0) { - tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]); - } else -#endif - { - tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); - } + tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); } else { tcg_gen_movi_tl(cpu_LO[acc], 0); }