From patchwork Tue Nov 4 15:38:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 406654 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 84C2614009E for ; Wed, 5 Nov 2014 02:38:55 +1100 (AEDT) Received: from localhost ([::1]:41182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlgC5-0007a7-Fe for incoming@patchwork.ozlabs.org; Tue, 04 Nov 2014 10:38:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59282) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlgBX-0006ux-Ql for qemu-devel@nongnu.org; Tue, 04 Nov 2014 10:38:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlgBQ-0007wj-On for qemu-devel@nongnu.org; Tue, 04 Nov 2014 10:38:19 -0500 Received: from relay1.mentorg.com ([192.94.38.131]:56138) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlgBQ-0007wf-JY for qemu-devel@nongnu.org; Tue, 04 Nov 2014 10:38:12 -0500 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=SVR-IES-FEM-01.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1XlgBP-0005AI-MY from Maciej_Rozycki@mentor.com ; Tue, 04 Nov 2014 07:38:11 -0800 Received: from localhost (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server (TLS) id 14.3.181.6; Tue, 4 Nov 2014 15:38:10 +0000 Date: Tue, 4 Nov 2014 15:38:05 +0000 From: "Maciej W. Rozycki" To: Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 192.94.38.131 Cc: Leon Alrae , Aurelien Jarno Subject: [Qemu-devel] [PATCH] mips: Add macros for CP0.Config3 and CP0.Config4 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Define macros for CP0.Config3 and CP0.Config4 bits. These used to be exhaustive as at MIPS32r3, but more bits may have been added since. Signed-off-by: Maciej W. Rozycki --- More can be added later on. For the time being, please apply. Maciej qemu-mips-config.diff Index: qemu-git-trunk/target-mips/cpu.h =================================================================== --- qemu-git-trunk.orig/target-mips/cpu.h 2014-11-02 01:08:26.527563002 +0000 +++ qemu-git-trunk/target-mips/cpu.h 2014-11-02 01:09:03.528200583 +0000 @@ -362,19 +362,34 @@ struct CPUMIPSState { #define CP0C2_SA 0 int32_t CP0_Config3; #define CP0C3_M 31 +#define CP0C3_BPG 30 +#define CP0C3_CMCGR 29 +#define CP0C3_IPLW 21 +#define CP0C3_MMAR 18 +#define CP0C3_MCU 17 #define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ISA 14 #define CP0C3_ULRI 13 +#define CP0C3_RXI 12 +#define CP0C3_DSP2P 11 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 #define CP0C3_VInt 5 #define CP0C3_SP 4 +#define CP0C3_CDMM 3 #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 int32_t CP0_Config4; int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 +#define CP0C4_KScrExist 16 +#define CP0C4_MMUExtDef 14 +#define CP0C4_FTLBPageSize 8 +#define CP0C4_FTLBWays 4 +#define CP0C4_FTLBSets 0 +#define CP0C4_MMUSizeExt 0 int32_t CP0_Config5; int32_t CP0_Config5_rw_bitmask; #define CP0C5_M 31