From patchwork Wed Jun 3 06:58:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 479777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D4C00140295 for ; Wed, 3 Jun 2015 16:59:44 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=U8yupUst; dkim-atps=neutral Received: from localhost ([::1]:33704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z02eN-0004QK-5B for incoming@patchwork.ozlabs.org; Wed, 03 Jun 2015 02:59:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z02e4-00048f-3m for qemu-devel@nongnu.org; Wed, 03 Jun 2015 02:59:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z02dy-0006wN-2b for qemu-devel@nongnu.org; Wed, 03 Jun 2015 02:59:24 -0400 Received: from mail-pd0-x22e.google.com ([2607:f8b0:400e:c02::22e]:34483) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z02dx-0006vw-Mw for qemu-devel@nongnu.org; Wed, 03 Jun 2015 02:59:17 -0400 Received: by pdbki1 with SMTP id ki1so930550pdb.1 for ; Tue, 02 Jun 2015 23:59:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=xWWo8j5EYEtR5GwF3cA7EhGEyjXNiy4IKHn6auGtDns=; b=U8yupUstPfi9H13mhosD/YwZXoL7yjZZHqLF/mv/fduSFUtU9DVEfMLvxjk8ZKvXXn A1Wgl2v37859l474XmvIzvYhU1KzjnbqijeSDjyTL4B7UoquEhfZ+BujFgZ9RiLwBIzI dsgwTNSDbM+X4ubPGoo2VzDdUM2RjGWyBXszWtFUiVWhMAw+qv2eNjOrvYTTg80G+R5g NvrvZFuArKWHinQAyheI/eelbNTaB/l1Lfd3JS7/WBmIEsKtLRBQIRMTJ75lUZTNPADy cG43dLPjX7QX6Rxz2jWsY8D5d5N/RGEiNsKz5rm8of5LaSAN8IP2aVK6hu6jRUzjWGG0 8+Pw== X-Received: by 10.68.191.229 with SMTP id hb5mr19471933pbc.126.1433314756817; Tue, 02 Jun 2015 23:59:16 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id nq2sm19858368pdb.70.2015.06.02.23.59.13 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 02 Jun 2015 23:59:16 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, edgar.iglesias@xilinx.com Date: Wed, 3 Jun 2015 16:58:40 +1000 Message-Id: X-Mailer: git-send-email 2.1.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22e Cc: peter.crosthwaite@xilinx.com, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v1 3/8] target-microblaze: Convert endi to a CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Originally the endi PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/microblaze/petalogix_ml605_mmu.c | 2 +- target-microblaze/cpu-qom.h | 1 + target-microblaze/cpu.c | 4 +++- target-microblaze/cpu.h | 2 +- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 995a579..5f341c4 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu) env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ - env->pvr.regs[0] |= PVR0_ENDI; env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); env->pvr.regs[4] = 0xc56b8000; env->pvr.regs[5] = 0xc56be000; @@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine) object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); object_property_set_bool(OBJECT(cpu), true, "dcache-writeback", &error_abort); + object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort); object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); /* Attach emulated BRAM through the LMB. */ diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index af6739f..85b8f75 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU { uint8_t usefpu; bool usemmu; bool dcache_writeback; + bool endi; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 2a1ff64..f40df43 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -114,7 +114,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) | - (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0); + (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) | + (cpu->cfg.endi ? PVR0_ENDI_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); @@ -174,6 +175,7 @@ static Property mb_properties[] = { DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.usemmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), + DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 36d5120..88e6a2a 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState; #define PVR0_USE_DCACHE_MASK 0x01000000 #define PVR0_USE_MMU_MASK 0x00800000 #define PVR0_USE_BTC 0x00400000 -#define PVR0_ENDI 0x00200000 +#define PVR0_ENDI_MASK 0x00200000 #define PVR0_FAULT 0x00100000 #define PVR0_VERSION_MASK 0x0000FF00 #define PVR0_USER1_MASK 0x000000FF