From patchwork Sat Mar 24 18:59:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 148534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 55A87B6EE7 for ; Sun, 25 Mar 2012 05:59:41 +1100 (EST) Received: from localhost ([::1]:37405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBWBf-0007Xv-B0 for incoming@patchwork.ozlabs.org; Sat, 24 Mar 2012 14:59:39 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBWBW-0007XY-Vg for qemu-devel@nongnu.org; Sat, 24 Mar 2012 14:59:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SBWBU-0005K9-RG for qemu-devel@nongnu.org; Sat, 24 Mar 2012 14:59:30 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:61280) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBWBU-0005HX-ID for qemu-devel@nongnu.org; Sat, 24 Mar 2012 14:59:28 -0400 Received: by mail-iy0-f173.google.com with SMTP id j26so7401858iaf.4 for ; Sat, 24 Mar 2012 11:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:from:date:message-id:subject:to:content-type; bh=UTFauBGByW6OPBK8bucLFgBYOwzriXS9jQkAwsOM8oo=; b=VR6RHRArX/4ECpOky+Gr6HgSXSNozwEVEoJGQVWjzcdVQ9el1qL68ybTI8hIPGviyD Lip7vuvx10oKMyocorOsaiy05KhRclYSbm3NXR1QLrUoTT5qgBlsa4g995VyUaeMKtKa yo3WspmNI0xfc1LflRo+I7/KiWTTFPEMcAoDU8M1tQF3CxJFzjo+6foLx73pp5xwOsVf lFOBhk+Ex24+lxPCP6CYIdim/G3ym0rg737vLD9QseQ3wc2vIjT2gB2iDvMXB9zVv9ZX DQ9RsVME4Dczn2ssBayZxVTFAAVpziEVCCkNuUSGKB3Vfbjsgp6ZsxoYxl5wZISu5ji1 RX9w== Received: by 10.50.156.135 with SMTP id we7mr2086349igb.0.1332615567611; Sat, 24 Mar 2012 11:59:27 -0700 (PDT) MIME-Version: 1.0 Received: by 10.50.75.41 with HTTP; Sat, 24 Mar 2012 11:59:07 -0700 (PDT) From: Blue Swirl Date: Sat, 24 Mar 2012 18:59:07 +0000 Message-ID: To: qemu-devel , Paul Brook , Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.173 Subject: [Qemu-devel] [PATCH 1/6] arm: move neon_tbl to neon_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add an explicit CPUARMState parameter instead of relying on AREG0 and move neon_tbl to neon_helper.c. Signed-off-by: Blue Swirl --- target-arm/helper.h | 2 +- target-arm/neon_helper.c | 22 ++++++++++++++++++++++ target-arm/op_helper.c | 22 ---------------------- target-arm/translate.c | 4 ++-- 4 files changed, 25 insertions(+), 25 deletions(-) tmp = neon_load_reg(rd, 1); @@ -6349,7 +6349,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins tcg_gen_movi_i32(tmp, 0); } tmp3 = neon_load_reg(rm, 1); - gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5); + gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5); tcg_temp_free_i32(tmp5); tcg_temp_free_i32(tmp4); neon_store_reg(rd, 0, tmp2); diff --git a/target-arm/helper.h b/target-arm/helper.h index 16dd5fc..40529eb 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -141,7 +141,7 @@ DEF_HELPER_2(recpe_f32, f32, f32, env) DEF_HELPER_2(rsqrte_f32, f32, f32, env) DEF_HELPER_2(recpe_u32, i32, i32, env) DEF_HELPER_2(rsqrte_u32, i32, i32, env) -DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32) +DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32) DEF_HELPER_2(add_cc, i32, i32, i32) DEF_HELPER_2(adc_cc, i32, i32, i32) diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c index 1e02d61..e3c08c2 100644 --- a/target-arm/neon_helper.c +++ b/target-arm/neon_helper.c @@ -2015,3 +2015,25 @@ void HELPER(neon_zip16)(CPUARMState *env, uint32_t rd, uint32_t rm) env->vfp.regs[rm] = make_float64(m0); env->vfp.regs[rd] = make_float64(d0); } + +uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, + uint32_t rn, uint32_t maxindex) +{ + uint32_t val; + uint32_t tmp; + int index; + int shift; + uint64_t *table; + table = (uint64_t *)&env->vfp.regs[rn]; + val = 0; + for (shift = 0; shift < 32; shift += 8) { + index = (ireg >> shift) & 0xff; + if (index < maxindex) { + tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; + val |= tmp << shift; + } else { + val |= def & (0xff << shift); + } + } + return val; +} diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index c728432..f4c0123 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -31,28 +31,6 @@ static void raise_exception(int tt) } #endif -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, - uint32_t rn, uint32_t maxindex) -{ - uint32_t val; - uint32_t tmp; - int index; - int shift; - uint64_t *table; - table = (uint64_t *)&env->vfp.regs[rn]; - val = 0; - for (shift = 0; shift < 32; shift += 8) { - index = (ireg >> shift) & 0xff; - if (index < maxindex) { - tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; - val |= tmp << shift; - } else { - val |= def & (0xff << shift); - } - } - return val; -} - #if !defined(CONFIG_USER_ONLY) #include "softmmu_exec.h" diff --git a/target-arm/translate.c b/target-arm/translate.c index 81725d1..72d33a9 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6340,7 +6340,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins tmp2 = neon_load_reg(rm, 0); tmp4 = tcg_const_i32(rn); tmp5 = tcg_const_i32(n); - gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5); + gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5); tcg_temp_free_i32(tmp); if (insn & (1 << 6)) {