diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 314d6ac..2ee59d5 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -491,6 +491,7 @@ enum {
     IR_ZERO = 31,
 };

+#ifndef NO_CPU_IO_DEFS
 CPUAlphaState * cpu_alpha_init (const char *cpu_model);
 int cpu_alpha_exec(CPUAlphaState *s);
 /* you can call this signal handler from your SIGBUS and SIGSEGV
@@ -511,6 +512,7 @@ int cpu_alpha_mtpr (CPUState *env, int iprn,
uint64_t val, uint64_t *oldvalp);
 void pal_init (CPUState *env);
 void call_pal (CPUState *env);
 #endif
+#endif

 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1e34541..098790e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -208,6 +208,7 @@ typedef struct CPUARMState {
     struct arm_boot_info *boot_info;
 } CPUARMState;

+#ifndef NO_CPU_IO_DEFS
 CPUARMState *cpu_arm_init(const char *cpu_model);
 void arm_translate_init(void);
 int cpu_arm_exec(CPUARMState *s);
@@ -231,6 +232,7 @@ static inline void cpu_set_tls(CPUARMState *env,
target_ulong newtls)
 {
   env->cp15.c13_tls2 = newtls;
 }
+#endif

 #define CPSR_M (0x1f)
 #define CPSR_T (1 << 5)
@@ -329,6 +331,7 @@ enum arm_cpu_mode {
 #define ARM_IWMMXT_wCGR2	10
 #define ARM_IWMMXT_wCGR3	11

+#ifndef NO_CPU_IO_DEFS
 enum arm_features {
     ARM_FEATURE_VFP,
     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
@@ -395,6 +398,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 #define ARM_CPUID_CORTEXA9    0x410fc090
 #define ARM_CPUID_CORTEXM3    0x410fc231
 #define ARM_CPUID_ANY         0xffffffff
+#endif

 #if defined(CONFIG_USER_ONLY)
 #define TARGET_PAGE_BITS 12
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 063a240..8ea803b 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -158,6 +158,7 @@ typedef struct CPUCRISState {
 	CPU_COMMON
 } CPUCRISState;

+#ifndef NO_CPU_IO_DEFS
 CPUCRISState *cpu_cris_init(const char *cpu_model);
 int cpu_cris_exec(CPUCRISState *s);
 void cpu_cris_close(CPUCRISState *s);
@@ -195,6 +196,7 @@ enum {
     CC_OP_ASR,
     CC_OP_LZ
 };
+#endif

 /* CRIS uses 8k pages.  */
 #define TARGET_PAGE_BITS 13
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 548ab80..8aad50e 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -720,6 +720,7 @@ typedef struct CPUX86State {
     uint16_t fpregs_format_vmstate;
 } CPUX86State;

+#ifndef NO_CPU_IO_DEFS
 CPUX86State *cpu_x86_init(const char *cpu_model);
 int cpu_x86_exec(CPUX86State *s);
 void cpu_x86_close(CPUX86State *s);
@@ -863,9 +864,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 uint64_t cpu_get_apic_base(CPUX86State *env);
 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
-#ifndef NO_CPU_IO_DEFS
 uint8_t cpu_get_apic_tpr(CPUX86State *env);
-#endif

 /* hw/pc.c */
 void cpu_smm_update(CPUX86State *env);
@@ -874,6 +873,7 @@ uint64_t cpu_get_tsc(CPUX86State *env);
 /* used to debug */
 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
+#endif

 #define TARGET_PAGE_BITS 12

diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index b2f37ec..ae20fa4 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -114,6 +114,7 @@ typedef struct CPUM68KState {
     uint32_t features;
 } CPUM68KState;

+#ifndef NO_CPU_IO_DEFS
 void m68k_tcg_init(void);
 CPUM68KState *cpu_m68k_init(const char *cpu_model);
 int cpu_m68k_exec(CPUM68KState *s);
@@ -138,6 +139,7 @@ enum {
     CC_OP_SUBX,  /* CC_DEST = result, CC_SRC = source */
     CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
 };
+#endif

 #define CCF_C 0x01
 #define CCF_V 0x02
@@ -151,6 +153,9 @@ enum {
 #define SR_S  0x2000
 #define SR_T  0x8000

+#define M68K_FPCR_PREC (1 << 6)
+
+#ifndef NO_CPU_IO_DEFS
 #define M68K_SSP    0
 #define M68K_USP    1

@@ -171,8 +176,6 @@ void m68k_set_irq_level(CPUM68KState *env, int
level, uint8_t vector);
 void m68k_set_macsr(CPUM68KState *env, uint32_t val);
 void m68k_switch_sp(CPUM68KState *env);

-#define M68K_FPCR_PREC (1 << 6)
-
 void do_m68k_semihosting(CPUM68KState *env, int nr);

 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
@@ -201,6 +204,7 @@ static inline int m68k_feature(CPUM68KState *env,
int feature)
 void m68k_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

 void register_m68k_insns (CPUM68KState *env);
+#endif

 #ifdef CONFIG_USER_ONLY
 /* Linux uses 8k pages.  */
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index ec2ca18..07a9ef1 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -233,6 +233,7 @@ typedef struct CPUMBState {
     CPU_COMMON
 } CPUMBState;

+#ifndef NO_CPU_IO_DEFS
 CPUState *cpu_mb_init(const char *cpu_model);
 int cpu_mb_exec(CPUState *s);
 void cpu_mb_close(CPUState *s);
@@ -248,6 +249,7 @@ enum {
     CC_OP_FLAGS,
     CC_OP_CMP,
 };
+#endif

 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 #define TARGET_PAGE_BITS 12
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7285636..ac3fde6 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -480,6 +480,7 @@ struct CPUMIPSState {
 };

 #if !defined(CONFIG_USER_ONLY)
+#ifndef NO_CPU_IO_DEFS
 int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t
*physical, int *prot,
                         target_ulong address, int rw, int access_type);
 int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t
*physical, int *prot,
@@ -490,6 +491,7 @@ void r4k_helper_tlbwi (void);
 void r4k_helper_tlbwr (void);
 void r4k_helper_tlbp (void);
 void r4k_helper_tlbr (void);
+#endif

 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int unused, int size);
@@ -584,6 +586,7 @@ enum {
 /* Dummy exception for conditional stores.  */
 #define EXCP_SC 0x100

+#ifndef NO_CPU_IO_DEFS
 int cpu_mips_exec(CPUMIPSState *s);
 CPUMIPSState *cpu_mips_init(const char *cpu_model);
 //~ uint32_t cpu_mips_get_clock (void);
@@ -610,6 +613,7 @@ void r4k_invalidate_tlb (CPUState *env, int idx,
int use_extra);
 target_phys_addr_t cpu_mips_translate_address (CPUState *env,
target_ulong address,
 		                               int rw);
 #endif
+#endif

 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 {
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 2ad4486..3a410d5 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -701,6 +701,7 @@ struct CPUPPCState {
     int (*osi_call)(struct CPUPPCState *env);
 };

+#ifndef NO_CPU_IO_DEFS
 #if !defined(CONFIG_USER_ONLY)
 /* Context used internally during MMU translations */
 typedef struct mmu_ctx_t mmu_ctx_t;
@@ -763,7 +764,6 @@ const ppc_def_t *cpu_ppc_find_by_name (const char *name);
 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);

 /* Time-base and decrementer management */
-#ifndef NO_CPU_IO_DEFS
 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
@@ -797,7 +797,6 @@ void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
 #endif
 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
 #endif
-#endif

 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
 {
@@ -820,6 +819,7 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState
*env, int gprn)
 /* Device control registers */
 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
+#endif

 #define cpu_init cpu_ppc_init
 #define cpu_exec cpu_ppc_exec
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index dd407b2..ffa2a3b 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -66,6 +66,7 @@ typedef struct CPUS390XState {
     CPU_COMMON
 } CPUS390XState;

+#ifndef NO_CPU_IO_DEFS
 #if defined(CONFIG_USER_ONLY)
 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 {
@@ -74,6 +75,7 @@ static inline void cpu_clone_regs(CPUState *env,
target_ulong newsp)
     env->regs[0] = 0;
 }
 #endif
+#endif

 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user
@@ -84,6 +86,7 @@ static inline int cpu_mmu_index (CPUState *env)
     return 0;
 }

+#ifndef NO_CPU_IO_DEFS
 CPUS390XState *cpu_s390x_init(const char *cpu_model);
 int cpu_s390x_exec(CPUS390XState *s);
 void cpu_s390x_close(CPUS390XState *s);
@@ -96,6 +99,7 @@ int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong
address, int rw,
                               int mmu_idx, int is_softmuu);
 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
+#endif

 #define TARGET_PAGE_BITS 12

diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index f8b1680..81b80a3 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -159,6 +159,7 @@ typedef struct CPUSH4State {
     memory_content **movcal_backup_tail;
 } CPUSH4State;

+#ifndef NO_CPU_IO_DEFS
 CPUSH4State *cpu_sh4_init(const char *cpu_model);
 int cpu_sh4_exec(CPUSH4State * s);
 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
@@ -185,6 +186,7 @@ static inline void cpu_set_tls(CPUSH4State *env,
target_ulong newtls)
 void cpu_load_tlb(CPUSH4State * env);

 #include "softfloat.h"
+#endif

 #define cpu_init cpu_sh4_init
