From patchwork Wed Jun 17 00:36:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 485234 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DB478140218 for ; Wed, 17 Jun 2015 10:38:24 +1000 (AEST) Received: from localhost ([::1]:43455 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z51N1-00075D-3j for incoming@patchwork.ozlabs.org; Tue, 16 Jun 2015 20:38:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z51Kr-0002nI-Iy for qemu-devel@nongnu.org; Tue, 16 Jun 2015 20:36:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z51Ko-00031V-9n for qemu-devel@nongnu.org; Tue, 16 Jun 2015 20:36:09 -0400 Received: from mail-ob0-f169.google.com ([209.85.214.169]:34918) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z51Ko-00031P-3n for qemu-devel@nongnu.org; Tue, 16 Jun 2015 20:36:06 -0400 Received: by obbgp2 with SMTP id gp2so22900482obb.2 for ; Tue, 16 Jun 2015 17:36:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Jd5hoWjD7h5ZCmL+kIGL0reFc5OKq7Cq3k/yGQV8els=; b=lIwwlam0UJCdN0+y2/9bwh0DxH6uPSYkdAuyiHcf75CO2blRweJkTrrM1+BPbeskia 7/cjaDr4dBJlbsCN88934/cIvCo17LZCzm9rEbjHYsm2dH2XRHyMjC9OJdl9kZuT1PCA uG7v6bdJsTSu5dnbZUovS/u5euqW3DuUGYM2bc47mrasF8NIraH5jvTcQJmy01y+Tdtv 7l7y7cHrDpgtt/y3e3XUJbm44eDsEXOQ/CmyZ5nY91uuejfAU+sBWJFW4FMiZv3dlgKC SFKpXIKumP1lY20Z/xdAuH0bKjfaMZsq4mb6qlJJe2/GEE4YbMz1sB2jJ8Nk4dpw8HNQ tzJg== X-Gm-Message-State: ALoCoQlFSFOoWxwQJZewA1Lso0vo7bH6xCONPswOJB/dcL82Yfz6ns9DVff42wOnPEiXnY/Z5KG+ X-Received: by 10.202.129.70 with SMTP id c67mr2358127oid.42.1434501365426; Tue, 16 Jun 2015 17:36:05 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id bq1sm1383200obb.0.2015.06.16.17.36.04 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jun 2015 17:36:04 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Tue, 16 Jun 2015 17:36:04 -0700 Message-Id: <9f248950b803a08c8b3c978931663182f7e882e7.1434501320.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.4.3.3.g905f831 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.169 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v3 1/7] target-arm/helper.c: define MPUIR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Signed-off-by: Peter Crosthwaite --- changed since v2 (PMM review): Fix commit message wording issues. change assertion to realize error. allow 0 regions. raise error of >255 memory regions. changed since v1: Add #regions configuration conditionalize MPUIR existence target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 18 ++++++++++++++++++ target-arm/helper.c | 10 ++++++++++ 3 files changed, 30 insertions(+) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 072aa9b..3cbc4a0 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -105,6 +105,8 @@ typedef struct ARMCPU { /* CPU has memory protection unit */ bool has_mpu; + /* PMSAv7 MPU number of supported regions */ + uint32_t pmsav7_dregion; /* PSCI conduit used to invoke PSCI methods * 0 - disabled, 1 - smc, 2 - hvc diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7496983..a3d702f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -457,6 +457,9 @@ static Property arm_cpu_has_el3_property = static Property arm_cpu_has_mpu_property = DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); +static Property arm_cpu_pmsav7_dregion_property = + DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); + static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -488,6 +491,11 @@ static void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + qdev_property_add_static(DEVICE(obj), + &arm_cpu_pmsav7_dregion_property, + &error_abort); + } } } @@ -580,6 +588,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) unset_feature(env, ARM_FEATURE_MPU); } + if (arm_feature(env, ARM_FEATURE_MPU) && + arm_feature(env, ARM_FEATURE_V7)) { + uint32_t nr = cpu->pmsav7_dregion; + + if (nr > 0xff) { + error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr); + return; + } + } + register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu); diff --git a/target-arm/helper.c b/target-arm/helper.c index 00509b1..685f972 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3465,6 +3465,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, }; + /* MPUIR is specific to PMSA V6+ */ + ARMCPRegInfo id_mpuir_reginfo = { + .name = "MPUIR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->pmsav7_dregion << 8 + }; ARMCPRegInfo crn0_wi_reginfo = { .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, @@ -3487,6 +3494,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) r->access = PL1_RW; } id_tlbtr_reginfo.access = PL1_RW; + id_tlbtr_reginfo.access = PL1_RW; } if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); @@ -3496,6 +3504,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_cp_reginfo); if (!arm_feature(env, ARM_FEATURE_MPU)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); } }