From patchwork Thu Feb 25 19:47:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 1444590 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dmk8S2X1wz9sBJ for ; Fri, 26 Feb 2021 06:57:12 +1100 (AEDT) Received: from localhost ([::1]:59974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFMl4-0000HD-AT for incoming@patchwork.ozlabs.org; Thu, 25 Feb 2021 14:57:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFMk5-0000GN-7t; Thu, 25 Feb 2021 14:56:09 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:44108) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFMk1-0000XH-Km; Thu, 25 Feb 2021 14:56:09 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A64F1746396; Thu, 25 Feb 2021 20:56:00 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 15F3E746334; Thu, 25 Feb 2021 20:56:00 +0100 (CET) Message-Id: <9d0d42f241616eb2c5ac1485bb97723cc0316f60.1614282456.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v4 1/6] vt82c686: Implement control of serial port io ranges via config regs Date: Thu, 25 Feb 2021 20:47:36 +0100 MIME-Version: 1.0 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-Spam-Probability: 8% Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Paolo Bonzini , f4bug@amsat.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In VIA super south bridge the io ranges of superio components (parallel and serial ports and FDC) can be controlled by superio config registers to set their base address and enable/disable them. This is not easy to implement in QEMU because ISA emulation is only designed to set io base address once on creating the device and io ranges are registered at creation and cannot easily be disabled or moved later. In this patch we hack around that but only for serial ports because those have a single io range at port base that's relatively easy to handle and it's what guests actually use and set address different than the default. We do not attempt to handle controlling the parallel and FDC regions because those have multiple io ranges so handling them would be messy and guests either don't change their deafult or don't care. We could even get away with disabling and not emulating them, but since they are already there, this patch leaves them mapped at their default address just in case this could be useful for a guest in the future. Signed-off-by: BALATON Zoltan --- hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 05d084f698..a3353ec5db 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -252,8 +252,24 @@ static const TypeInfo vt8231_pm_info = { typedef struct SuperIOConfig { uint8_t regs[0x100]; MemoryRegion io; + ISASuperIODevice *superio; + MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS]; } SuperIOConfig; +static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent, + int offs) +{ + MemoryRegion *subregion, *mr = NULL; + + QTAILQ_FOREACH(subregion, &parent->subregions, subregions_link) { + if (subregion->addr == offs) { + mr = subregion; + break; + } + } + return mr; +} + static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { @@ -279,7 +295,53 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, case 0xfd ... 0xff: /* ignore write to read only registers */ return; - /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ + case 0xe2: + { + data &= 0x1f; + if (data & BIT(2)) { /* Serial port 1 enable */ + ISADevice *dev = sc->superio->serial[0]; + if (!memory_region_is_mapped(sc->serial_io[0])) { + memory_region_add_subregion(isa_address_space_io(dev), + dev->ioport_id, sc->serial_io[0]); + } + } else { + MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]); + if (memory_region_is_mapped(sc->serial_io[0])) { + memory_region_del_subregion(io, sc->serial_io[0]); + } + } + if (data & BIT(3)) { /* Serial port 2 enable */ + ISADevice *dev = sc->superio->serial[1]; + if (!memory_region_is_mapped(sc->serial_io[1])) { + memory_region_add_subregion(isa_address_space_io(dev), + dev->ioport_id, sc->serial_io[1]); + } + } else { + MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]); + if (memory_region_is_mapped(sc->serial_io[1])) { + memory_region_del_subregion(io, sc->serial_io[1]); + } + } + break; + } + case 0xe7: /* Serial port 1 io base address */ + { + data &= 0xfe; + sc->superio->serial[0]->ioport_id = data << 2; + if (memory_region_is_mapped(sc->serial_io[0])) { + memory_region_set_address(sc->serial_io[0], data << 2); + } + break; + } + case 0xe8: /* Serial port 2 io base address */ + { + data &= 0xfe; + sc->superio->serial[1]->ioport_id = data << 2; + if (memory_region_is_mapped(sc->serial_io[1])) { + memory_region_set_address(sc->serial_io[1], data << 2); + } + break; + } default: qemu_log_mask(LOG_UNIMP, "via_superio_cfg: unimplemented register 0x%x\n", idx); @@ -385,6 +447,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp) DeviceState *dev = DEVICE(d); ISABus *isa_bus; qemu_irq *isa_irq; + ISASuperIOClass *ic; int i; qdev_init_gpio_out(dev, &s->cpu_intr, 1); @@ -394,7 +457,9 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); + s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus, + TYPE_VT82C686B_SUPERIO)); + ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio); mc146818_rtc_init(isa_bus, 2000, NULL); for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { @@ -412,6 +477,21 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp) */ memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, &s->superio_cfg.io); + + /* Grab io regions of serial devices so we can control them */ + for (i = 0; i < ic->serial.count; i++) { + ISADevice *sd = s->superio_cfg.superio->serial[i]; + MemoryRegion *io = isa_address_space_io(sd); + MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id); + if (!mr) { + error_setg(errp, "Could not get io region for serial %d", i); + return; + } + s->superio_cfg.serial_io[i] = mr; + if (memory_region_is_mapped(mr)) { + memory_region_del_subregion(io, mr); + } + } } static void via_class_init(ObjectClass *klass, void *data)