From patchwork Mon Jun 1 18:04:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 479127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CD9E1140DCC for ; Tue, 2 Jun 2015 04:07:06 +1000 (AEST) Received: from localhost ([::1]:53746 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU76-0007Ub-Lr for incoming@patchwork.ozlabs.org; Mon, 01 Jun 2015 14:07:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4b-0002sy-LC for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzU4X-0008EA-Dw for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:29 -0400 Received: from mail-ob0-f176.google.com ([209.85.214.176]:36309) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4X-0008E4-Ax for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:25 -0400 Received: by obbea2 with SMTP id ea2so109626559obb.3 for ; Mon, 01 Jun 2015 11:04:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=t/uSSrQ+wq+V/qi8x4n0Dlcb1PNeNX3AfOWxwffVBNY=; b=jBzY2bhHyRuR/8CfKk0z/tx/xV9s6/fQttu+vN601n5IMk0WeuDF+iqFfFZzOEVex4 3sLkZQ7yA9+hWI7pIslEWyMq+aQQwxkgGatk6K3k6aJYH14gCJzUg2urjxxORoLqDuQ3 /lltJmzfk+Nl0zZFNPbXokQdXmSRpDVA8vF4mTWWnwHWqYig7apVjlDpSTr1CY8NPfgW AUoUx64v21gOvE4pFCoiPnby9FnQeAvjgVeEj18ljtG1n7s8W2VqYM2OcalKSkX1am62 DcpKJajMNlD51RndTy2cSW+oOOiBr8hEhmzojKe70YzRTlSvnj4BEe89OIBcT8/TGdPC kZlQ== X-Gm-Message-State: ALoCoQl+Ft7fzZw3XekqRxUV5kUFaOS8P01BUE0zITaTxsOu1lFmb+j0CRB8CjUvBSntSmVP4bNI X-Received: by 10.202.91.212 with SMTP id p203mr3577410oib.108.1433181864953; Mon, 01 Jun 2015 11:04:24 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id f129sm8010529oic.19.2015.06.01.11.04.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Jun 2015 11:04:24 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 1 Jun 2015 11:04:23 -0700 Message-Id: <98f32d148a274a82e7cace3c9248bd01b9f196a5.1433180153.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.4.2.3.g2ffcb72 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.176 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v1 4/9] target-arm: Add registers for PMSAv7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org define the arm CP registers for PMSAv7 and their accessor functions. Signed-off-by: Peter Crosthwaite --- target-arm/cpu.h | 6 ++++++ target-arm/helper.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 09cc16d..9cb2e49 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -286,6 +286,12 @@ typedef struct CPUARMState { }; uint64_t par_el[4]; }; + + uint32_t c6_rgnr; + uint32_t c6_drbar[PMSAV7_MPU_NUM_REGIONS]; + uint32_t c6_drsr[PMSAV7_MPU_NUM_REGIONS]; + uint32_t c6_dracr[PMSAV7_MPU_NUM_REGIONS]; + uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index cb21bbf..f11efea 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1709,6 +1709,54 @@ static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); } +static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t *u32p = (void *)env + ri->fieldoffset; + + u32p += env->cp15.c6_rgnr; + return *u32p; +} + +static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + uint32_t *u32p = (void *)env + ri->fieldoffset; + + u32p += env->cp15.c6_rgnr; + tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */ + *u32p = value; +} + +static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int i; + uint32_t *u32p = (void *)env + ri->fieldoffset; + + for (i = 0; i < 16; ++i) { + u32p[i] = 0; + } +} + +static const ARMCPRegInfo pmsav7_cp_reginfo[] = { + { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c6_drbar[0]), + .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c6_drsr[0]), + .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c6_dracr[0]), + .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, + { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), .resetvalue = 0, }, + REGINFO_SENTINEL +}; + static const ARMCPRegInfo pmsav5_cp_reginfo[] = { { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_ALIAS,