From patchwork Mon Jun 1 18:04:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 479126 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id F0B24140DCC for ; Tue, 2 Jun 2015 04:06:45 +1000 (AEST) Received: from localhost ([::1]:53744 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU6l-0006ld-Ml for incoming@patchwork.ozlabs.org; Mon, 01 Jun 2015 14:06:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37711) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4U-0002j9-DL for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzU4P-0008By-0L for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:22 -0400 Received: from mail-ob0-f171.google.com ([209.85.214.171]:34194) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4O-0008Bq-TL for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:16 -0400 Received: by obew15 with SMTP id w15so110069633obe.1 for ; Mon, 01 Jun 2015 11:04:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=R1VB8E/DWUoMleNMGkdvXIyQicrbGiQ8funL9u+PHc4=; b=GTFy3YcL3t/EWVLOsc8ZTBmTgdDpbqo2iMxnu8z7sryq/SU3uzRnJKIY1dU8SceJRH 85DfbOtcOaV5Hr026d2U7OYxBpknLfpgGz83wirBOSemVGP/p9ZAdUymgswJXBvqIwZe xYyCarzxetLPhNiGkHF52wF2KSxb93XbJ6grZKABWe5j66XM5gYq5N99n/OZyoZYXxDA AJwQfSTS91wkbaq+j15Jyck2H1z9Cds4tHUC41Dp7OdzbypZqjC6DhQFHoMoTJSYUlOu 8jGlPaYDiUrtLw5jqXMZzNTTeQ83oJQWlp+lgLFoufZnWt2wcboIV+tMotyCJst3tivD iBnA== X-Gm-Message-State: ALoCoQnTbJUx1ZSLsT5y/LMTwZy21B6kpN7+xebUOt+7ocBFiqiPlHFOXGTwDg/1O3P+SN97Lf2D X-Received: by 10.202.172.16 with SMTP id v16mr9977062oie.51.1433181856309; Mon, 01 Jun 2015 11:04:16 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id x3sm7979432obm.8.2015.06.01.11.04.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Jun 2015 11:04:15 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 1 Jun 2015 11:04:15 -0700 Message-Id: <93f61e11ec3444b7402072b76ad22267a3e166fd.1433180153.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.4.2.3.g2ffcb72 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.171 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v1 1/9] target-arm: Prepare support for Cortex-R5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU, and both thumb and ARM div instructions. Signed-off-by: Peter Crosthwaite --- target-arm/cpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4a888ab..4872d9c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -794,6 +794,32 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; } +static void cortex_r5_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); + set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_MPU); + cpu->midr = 0x411fc153; /* r1p3 */ + cpu->id_pfr0 = 0x0131; + cpu->id_pfr1 = 0x001; + cpu->id_dfr0 = 0x010400; + cpu->id_afr0 = 0x0; + cpu->id_mmfr0 = 0x0210030; + cpu->id_mmfr1 = 0x00000000; + cpu->id_mmfr2 = 0x01200000; + cpu->id_mmfr3 = 0x0211; + cpu->id_isar0 = 0x2101111; + cpu->id_isar1 = 0x13112111; + cpu->id_isar2 = 0x21232141; + cpu->id_isar3 = 0x01112131; + cpu->id_isar4 = 0x0010142; + cpu->id_isar5 = 0x0; +} + static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -1185,6 +1211,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, .class_init = arm_v7m_class_init }, + { .name = "cortex-r5", .initfn = cortex_r5_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn },