diff mbox series

[v4,4/8] target/mips: Add function to signal RI exception unless user only

Message ID 842278e9826c21da2a425feea040657af70a59cd.1537122775.git.noring@nocrew.org
State New
Headers show
Series target/mips: Support R5900 GCC programs in user mode | expand

Commit Message

Fredrik Noring Sept. 16, 2018, 3:04 p.m. UTC
The Linux kernel traps and emulates certain instructions. For user only,
QEMU is the kernel, so we emulate those traps by simply emulating the
instructions directly.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
 target/mips/translate.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Philippe Mathieu-Daudé Sept. 16, 2018, 11:45 p.m. UTC | #1
On 9/16/18 5:04 PM, Fredrik Noring wrote:
> The Linux kernel traps and emulates certain instructions. For user only,
> QEMU is the kernel, so we emulate those traps by simply emulating the
> instructions directly.
> 
> Signed-off-by: Fredrik Noring <noring@nocrew.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/mips/translate.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c35be0053b..77d678353e 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1887,6 +1887,20 @@ static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
>      }
>  }
>  
> +/*
> + * Unless user only, when the kernel emulates the code, a "reserved
> + * instruction" exception is generated if the CPU has corresponding
> + * flag set which indicates that the instruction has been removed.
> + */
> +static inline void check_insn_opc_user_only(DisasContext *ctx, int flags)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    if (unlikely(ctx->insn_flags & flags)) {
> +        generate_exception_end(ctx, EXCP_RI);
> +    }
> +#endif
> +}
> +
>  /* This code generates a "reserved instruction" exception if the
>     CPU does not support 64-bit paired-single (PS) floating point data type */
>  static inline void check_ps(DisasContext *ctx)
>
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c35be0053b..77d678353e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1887,6 +1887,20 @@  static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
     }
 }
 
+/*
+ * Unless user only, when the kernel emulates the code, a "reserved
+ * instruction" exception is generated if the CPU has corresponding
+ * flag set which indicates that the instruction has been removed.
+ */
+static inline void check_insn_opc_user_only(DisasContext *ctx, int flags)
+{
+#ifndef CONFIG_USER_ONLY
+    if (unlikely(ctx->insn_flags & flags)) {
+        generate_exception_end(ctx, EXCP_RI);
+    }
+#endif
+}
+
 /* This code generates a "reserved instruction" exception if the
    CPU does not support 64-bit paired-single (PS) floating point data type */
 static inline void check_ps(DisasContext *ctx)