From patchwork Wed Oct 21 10:17:38 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 36517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3F56AB7B9C for ; Wed, 21 Oct 2009 21:23:44 +1100 (EST) Received: from localhost ([127.0.0.1]:60265 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N0YM0-0008Ji-Oz for incoming@patchwork.ozlabs.org; Wed, 21 Oct 2009 06:23:40 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N0YGU-0006Hm-Ch for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:17:58 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N0YGP-0006Fj-Ay for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:17:57 -0400 Received: from [199.232.76.173] (port=43273 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N0YGO-0006FU-TJ for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:17:52 -0400 Received: from smtp.nokia.com ([192.100.122.233]:27328 helo=mgw-mx06.nokia.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N0YGN-0000V6-DX for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:17:52 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9LAHjbU013269 for ; Wed, 21 Oct 2009 13:17:48 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 21 Oct 2009 13:17:45 +0300 Received: from smtp.mgd.nokia.com ([65.54.30.8]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 21 Oct 2009 13:17:40 +0300 Received: from NOK-EUMSG-05.mgdnok.nokia.com ([65.54.30.90]) by nok-am1mhub-04.mgdnok.nokia.com ([65.54.30.8]) with mapi; Wed, 21 Oct 2009 12:17:23 +0200 From: To: Date: Wed, 21 Oct 2009 12:17:38 +0200 Thread-Topic: [PATCH 02/12] target-arm: optimize thumb 32bit multiply Thread-Index: AcpSN66huDAwjZCnRmi4PVF2JOEa9Q== Message-ID: <82376447-482D-43AA-99FA-73C4A7484615@nokia.com> Accept-Language: en, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en, en-US MIME-Version: 1.0 X-OriginalArrivalTime: 21 Oct 2009 10:17:40.0577 (UTC) FILETIME=[B8834510:01CA5237] X-Nokia-AV: Clean X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH 02/12] target-arm: optimize thumb 32bit multiply X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Current implementation of thumb mul instruction is implemented as a 32x32->64 multiply which then uses only 32 least significant bits of the result. Replace that with a simple 32x32->32 multiply. Signed-off-by: Juha Riihimäki Acked-by: Laurent Desnogues --- break; diff --git a/target-arm/translate.c b/target-arm/translate.c index bda105e..3ea9d51 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -310,22 +310,6 @@ static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b) return tmp1; } -/* Unsigned 32x32->64 multiply. */ -static void gen_mull(TCGv a, TCGv b) -{ - TCGv_i64 tmp1 = tcg_temp_new_i64(); - TCGv_i64 tmp2 = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(tmp1, a); - tcg_gen_extu_i32_i64(tmp2, b); - tcg_gen_mul_i64(tmp1, tmp1, tmp2); - tcg_temp_free_i64(tmp2); - tcg_gen_trunc_i64_i32(a, tmp1); - tcg_gen_shri_i64(tmp1, tmp1, 32); - tcg_gen_trunc_i64_i32(b, tmp1); - tcg_temp_free_i64(tmp1); -} - /* Signed 32x32->64 multiply. */ static void gen_imull(TCGv a, TCGv b) { @@ -8358,7 +8342,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) gen_logic_CC(tmp); break; case 0xd: /* mul */ - gen_mull(tmp, tmp2); + tcg_gen_mul_i32(tmp, tmp, tmp2); if (!s->condexec_mask) gen_logic_CC(tmp);