From patchwork Thu Aug 13 11:02:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Fedin X-Patchwork-Id: 506967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E65F51402A3 for ; Thu, 13 Aug 2015 21:05:19 +1000 (AEST) Received: from localhost ([::1]:41815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPqJy-0007vh-0f for incoming@patchwork.ozlabs.org; Thu, 13 Aug 2015 07:05:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43702) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPqHB-0002iV-By for qemu-devel@nongnu.org; Thu, 13 Aug 2015 07:02:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZPqH9-0006HD-6t for qemu-devel@nongnu.org; Thu, 13 Aug 2015 07:02:25 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:34188) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPqH8-0006Gd-U5 for qemu-devel@nongnu.org; Thu, 13 Aug 2015 07:02:23 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NT000I1BPBXPN10@mailout4.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 13 Aug 2015 12:02:21 +0100 (BST) X-AuditID: cbfec7f5-f794b6d000001495-4d-55cc793dfe59 Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 75.98.05269.D397CC55; Thu, 13 Aug 2015 12:02:21 +0100 (BST) Received: from localhost ([106.109.131.169]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NT0003UXPBX3110@eusync1.samsung.com>; Thu, 13 Aug 2015 12:02:21 +0100 (BST) From: Pavel Fedin To: qemu-devel@nongnu.org Date: Thu, 13 Aug 2015 14:02:16 +0300 Message-id: <78eaa0a4d3e96b42cfae77ee3ffeebfa48651de2.1439462433.git.p.fedin@samsung.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-reply-to: References: In-reply-to: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCLMWRmVeSWpSXmKPExsVy+t/xy7q2lWdCDW7dUbF48fofo8X8LWdY LeacecBicbx3B4tF2+fv7BZ3X39mcWDz2DnrLrtHy5G3rB53ru1h83hybTNTAEsUl01Kak5m WWqRvl0CV8b0FS/YCy5HVhzvPMLYwPjeoYuRk0NCwERi2sEGNghbTOLCvfVANheHkMBSRokf O9+xQDjfGCWOzHnHCFLFJqAucfrrBxYQW0RAUuJ312lmkCJmgUeMEl+3nmEGSQgLeEksmTQR zGYRUJU4MekUO4jNKxAt8WnpNHaIdRoSi77MAVvNKWAusfXNbLChQgJmErc3PGbCJT6BkX8B I8MqRtHU0uSC4qT0XCO94sTc4tK8dL3k/NxNjJCw+7qDcekxq0OMAhyMSjy8Gx6dDhViTSwr rsw9xCjBwawkwnsv7UyoEG9KYmVValF+fFFpTmrxIUZpDhYlcd6Zu96HCAmkJ5akZqemFqQW wWSZODilGhj3nPoluXDumVkMs+fJn0rzaY4q9uL0PRkzy8q8MVu3I/X3ysgmZs3QbRNKPq17 cOTF3SWW/x7nCoSFxO/skTU41BN2Well0MozS/25/Dn1ru36V/2vW0SSo1Sq5QTj3MmSWS1H YkUuH1ydtTu1ZK+areChRaK/NsfebTg613/JomcPOu9WRSQpsRRnJBpqMRcVJwIAN6j9bzcC AAA= X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 210.118.77.14 Cc: Peter Maydell , Shlomo Pongratz , Shlomo Pongratz , Christoffer Dall , Eric Auger Subject: [Qemu-devel] [PATCH v9 5/5] hw/arm/virt: Add gicversion option to virt machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add gic_version to VirtMachineState, set it to value of the option and pass it around where necessary. Instantiate devices and fdt nodes according to the choice. max_cpus for virt machine increased to 126 (calculated from redistributor space available in the memory map). GICv2 compatibility check happens inside arm_gic_common_realize(). ITS regions are added to the memory map too, however currently they are not used, just reserved. Signed-off-by: Pavel Fedin --- hw/arm/virt.c | 111 +++++++++++++++++++++++++++++++++++++++++--------- include/hw/arm/fdt.h | 2 +- include/hw/arm/virt.h | 5 ++- 3 files changed, 96 insertions(+), 22 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 943e523..05bf130 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -49,6 +49,7 @@ #include "hw/platform-bus.h" #include "hw/arm/fdt.h" #include "kvm_arm.h" +#include "qapi/visitor.h" /* Number of external interrupt lines to configure the GIC with */ #define NUM_IRQS 256 @@ -78,6 +79,7 @@ typedef struct { typedef struct { MachineState parent; bool secure; + int32_t gic_version; } VirtMachineState; #define TYPE_VIRT_MACHINE "virt" @@ -108,6 +110,9 @@ static const MemMapEntry a15memmap[] = { [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, + [VIRT_ITS_CONTROL] = { 0x08020000, 0x00010000 }, + [VIRT_ITS_TRANSLATION] = { 0x08030000, 0x00010000 }, + [VIRT_GIC_REDIST] = { 0x08040000, 0x00FC0000 }, [VIRT_UART] = { 0x09000000, 0x00001000 }, [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] = { 0x09020000, 0x0000000a }, @@ -257,10 +262,13 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) * they are edge-triggered. */ ARMCPU *armcpu; + uint32_t max; uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; + /* Argument is 32 bit but 8 bits are reserved for flags */ + max = (vbi->smp_cpus >= 24) ? 24 : vbi->smp_cpus; irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, - GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1); + GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << max) - 1); qemu_fdt_add_subnode(vbi->fdt, "/timer"); @@ -284,6 +292,18 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) { int cpu; + /* + * From Documentation/devicetree/bindings/arm/cpus.txt + * On ARM v8 64-bit systems value should be set to 2, + * that corresponds to the MPIDR_EL1 register size. + * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + * in the system, #address-cells can be set to 1, since + * MPIDR_EL1[63:32] bits are not used for CPUs + * identification. + * + * Now GIC500 doesn't support affinities 2 & 3 so currently + * #address-cells can stay 1 until future GIC + */ qemu_fdt_add_subnode(vbi->fdt, "/cpus"); qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); @@ -320,25 +340,36 @@ static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle); } -static void fdt_add_gic_node(VirtBoardInfo *vbi) +static void fdt_add_gic_node(VirtBoardInfo *vbi, int type) { vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); qemu_fdt_add_subnode(vbi->fdt, "/intc"); - /* 'cortex-a15-gic' means 'GIC v2' */ - qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", - "arm,cortex-a15-gic"); qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); - qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", - 2, vbi->memmap[VIRT_GIC_DIST].base, - 2, vbi->memmap[VIRT_GIC_DIST].size, - 2, vbi->memmap[VIRT_GIC_CPU].base, - 2, vbi->memmap[VIRT_GIC_CPU].size); qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); + if (type == 3) { + qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", + "arm,gic-v3"); + qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", + 2, vbi->memmap[VIRT_GIC_DIST].base, + 2, vbi->memmap[VIRT_GIC_DIST].size, + 2, vbi->memmap[VIRT_GIC_REDIST].base, + 2, vbi->memmap[VIRT_GIC_REDIST].size); + } else { + /* 'cortex-a15-gic' means 'GIC v2' */ + qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", + "arm,cortex-a15-gic"); + qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", + 2, vbi->memmap[VIRT_GIC_DIST].base, + 2, vbi->memmap[VIRT_GIC_DIST].size, + 2, vbi->memmap[VIRT_GIC_CPU].base, + 2, vbi->memmap[VIRT_GIC_CPU].size); + } + qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); } @@ -361,18 +392,18 @@ static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) fdt_add_v2m_gic_node(vbi); } -static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) +static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type) { - /* We create a standalone GIC v2 */ + /* We create a standalone GIC */ DeviceState *gicdev; SysBusDevice *gicbusdev; const char *gictype; int i; - gictype = gic_class_name(); + gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); gicdev = qdev_create(NULL, gictype); - qdev_prop_set_uint32(gicdev, "revision", 2); + qdev_prop_set_uint32(gicdev, "revision", type); qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); /* Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec). @@ -381,7 +412,11 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) qdev_init_nofail(gicdev); gicbusdev = SYS_BUS_DEVICE(gicdev); sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); - sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); + if (type == 3) { + sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base); + } else { + sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); + } /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs, and the GIC's IRQ output to @@ -408,9 +443,11 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) pic[i] = qdev_get_gpio_in(gicdev, i); } - fdt_add_gic_node(vbi); + fdt_add_gic_node(vbi, type); - create_v2m(vbi, pic); + if (type == 2) { + create_v2m(vbi, pic); + } } static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) @@ -714,7 +751,10 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic) qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, nr_pcie_buses - 1); - qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", vbi->v2m_phandle); + if (vbi->v2m_phandle) { + qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", + vbi->v2m_phandle); + } qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base_ecam, 2, size_ecam); @@ -874,7 +914,7 @@ static void machvirt_init(MachineState *machine) create_flash(vbi); - create_gic(vbi, pic); + create_gic(vbi, pic, vms->gic_version); create_uart(vbi, pic); @@ -932,6 +972,26 @@ static void virt_set_secure(Object *obj, bool value, Error **errp) vms->secure = value; } +static void virt_get_gic_version(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + visit_type_int32(v, &vms->gic_version, name, errp); +} + +static void virt_set_gic_version(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + visit_type_int32(v, &vms->gic_version, name, errp); + if (vms->gic_version != 2 && vms->gic_version != 3) { + error_report ("Only GICv2 and GICv3 supported currently\n"); + exit(1); + } +} + static void virt_instance_init(Object *obj) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -944,6 +1004,14 @@ static void virt_instance_init(Object *obj) "Set on/off to enable/disable the ARM " "Security Extensions (TrustZone)", NULL); + + /* Default GIC type is v2 */ + vms->gic_version = 2; + object_property_add(obj, "gicversion", "int", virt_get_gic_version, + virt_set_gic_version, NULL, NULL, NULL); + object_property_set_description(obj, "gicversion", + "Set GIC version. " + "Valid values are 2 and 3", NULL); } static void virt_class_init(ObjectClass *oc, void *data) @@ -953,7 +1021,10 @@ static void virt_class_init(ObjectClass *oc, void *data) mc->name = TYPE_VIRT_MACHINE; mc->desc = "ARM Virtual Machine", mc->init = machvirt_init; - mc->max_cpus = 8; + /* Our maximum number of CPUs depends on how many redistributors + * we can fit into memory map + */ + mc->max_cpus = a15memmap[VIRT_GIC_REDIST].size / 0x20000; mc->has_dynamic_sysbus = true; mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; diff --git a/include/hw/arm/fdt.h b/include/hw/arm/fdt.h index c3d5015..dd794dd 100644 --- a/include/hw/arm/fdt.h +++ b/include/hw/arm/fdt.h @@ -29,6 +29,6 @@ #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 #define GIC_FDT_IRQ_PPI_CPU_START 8 -#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 +#define GIC_FDT_IRQ_PPI_CPU_WIDTH 24 #endif diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index d22fd8e..6c5a9c9 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -46,6 +46,10 @@ enum { VIRT_CPUPERIPHS, VIRT_GIC_DIST, VIRT_GIC_CPU, + VIRT_GIC_V2M, + VIRT_ITS_CONTROL, + VIRT_ITS_TRANSLATION, + VIRT_GIC_REDIST, VIRT_UART, VIRT_MMIO, VIRT_RTC, @@ -54,7 +58,6 @@ enum { VIRT_PCIE_MMIO, VIRT_PCIE_PIO, VIRT_PCIE_ECAM, - VIRT_GIC_V2M, VIRT_PLATFORM_BUS, };